Search Results
| Search type | Search syntax |
|---|---|
| Tags | [tag] |
| Exact | "words here" |
| Author |
user:1234 user:me (yours) |
| Score |
score:3 (3+) score:0 (none) |
| Answers |
answers:3 (3+) answers:0 (none) isaccepted:yes hasaccepted:no inquestion:1234 |
| Views | views:250 |
| Code | code:"if (foo != bar)" |
| Sections |
title:apples body:"apples oranges" |
| URL | url:"*.example.com" |
| Saves | in:saves |
| Status |
closed:yes duplicate:no migrated:no wiki:no |
| Types |
is:question is:answer |
| Exclude |
-[tag] -apples |
| For more details on advanced search visit our help page | |
Results tagged with vivado
Search options not deleted
user 103599
FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.
1
vote
Accepted
Simulation on VHDL failing
test_unit: branchcontrol port map(
PL => PL, BC => BC, PC => PC, AD => AD,
Flags => Flags, PCLoad => PCLoad,
PC => PCValue);
should be
test_unit: branchcontrol port map(
…
- 532
0
votes
Zynq - Configuring SPI clock to idle high
I also had some trouble with the Zynq SPI peripheral and as DoxyLover pointed out it has to do with the clock line being set to High-Z in Linux when data isn't being transferred. I solved this by brin …
- 532
1
vote
Simple binary adder works only partially
I can't say for sure this will help, but I find the "pipeline" process in the "adder" entity to be unusual. I would use an elsif on the rising_edge of clock and remove A and B from the sensitivity lis …
- 532
1
vote
Moving a large dataset from the PS to PL on a zynq device?
The interconnect between the Processing System and Programmable Logic is limited by the bus width of the AXI interface.
It sound like you are looking for a way of passing a buffer directly from softw …
- 532