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Results tagged with vivado
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user 103599
FPGA design suite by Xilinx. It is the successor to the ISE FPGA design suite.
1
vote
Accepted
Simulation on VHDL failing
test_unit: branchcontrol port map(
PL => PL, BC => BC, PC => PC, AD => AD,
Flags => Flags, PCLoad => PCLoad,
PC => PCValue);
should be
test_unit: branchcontrol port map(
…
- 532
0
votes
Zynq - Configuring SPI clock to idle high
I also had some trouble with the Zynq SPI peripheral and as DoxyLover pointed out it has to do with the clock line being set to High-Z in Linux when data isn't being transferred. I solved this by brin …
- 532
1
vote
Moving a large dataset from the PS to PL on a zynq device?
The interconnect between the Processing System and Programmable Logic is limited by the bus width of the AXI interface.
It sound like you are looking for a way of passing a buffer directly from softw …
- 532
1
vote
Simple binary adder works only partially
I can't say for sure this will help, but I find the "pipeline" process in the "adder" entity to be unusual. I would use an elsif on the rising_edge of clock and remove A and B from the sensitivity lis …
- 532