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Results tagged with xilinx
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user 103599
A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
0
votes
Zynq - Configuring SPI clock to idle high
I also had some trouble with the Zynq SPI peripheral and as DoxyLover pointed out it has to do with the clock line being set to High-Z in Linux when data isn't being transferred. I solved this by brin …
- 532
1
vote
How to interface UART with BRAM in xilinx virtex 5
Based on your second screen capture you are reading at addressb=1 NOT addressb=0.
RdB gets set high in the "reading" state and addressb gets incremented, but these values do not get read out of the …
- 532
1
vote
Simple binary adder works only partially
I can't say for sure this will help, but I find the "pipeline" process in the "adder" entity to be unusual. I would use an elsif on the rising_edge of clock and remove A and B from the sensitivity lis …
- 532
1
vote
Moving a large dataset from the PS to PL on a zynq device?
If this is the case I would suggest looking into using the Direct Memory Access (DMA) IPs provided by Xilinx. …
- 532