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Results tagged with verilog
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user 16047
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
2
votes
Using Memory values in Verilog / VHDL
See the Xilinx AXI Reference guide
and the AMBA AXI protocol reference.
In particular, see section A3.2: "Basic read and write transactions" which details how the valid/ready handshake protocol works …
- 5,412
1
vote
Accepted
How to send a packet every n clock cycles in verilog?
There are a couple of things to point out in your code.
1) you're driving the reg_read_en and reg_write_en signals in both always blocks.
always@(posedge clk_i or negedge resetn_i) begin
if (resetn …
- 5,412
1
vote
Xilinx XPS : On what bases the AXI master changes AWSIZE/ARSIZE....?
The SIZE bits specify the axi bus width. To do a shorter write, use the STRB bits to specify which bytes are valid.
See the axi spec, page A3-49
Write strobes
The WSTRB[n:0] signals when HIG …
- 5,412
2
votes
Accepted
Modelling Circuit from FSM using Verilog
You want to use a nonblocking assignment. These assignments change at the clock edge.
always @ (posedge c)
begin
q <= d;
q0 <= ~d;
end
In order to illustrate the implications of blocking …
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1
vote
2
answers
4k
views
What is a #delay inside a synchronous process used for?
I came across a synchronous process similar to this today, and immediately noticed the presence of the #delay:
`define dly #1
always @ (posedge fpga_sysclk_b or negedge reset_l) begin
if (!rese …
- 5,412
6
votes
Accepted
State based vs State-less design (in verilog)
Even though a design may be considered 'stateless' because there is no explicit state machine, you may still be actually coding a type of state mechanism without explicitly calling it that. For exampl …
- 5,412
2
votes
1
answer
4k
views
Is it possible to drive a net from two processes when the assignments are conditionally mutu...
In my experience, driving a net from two separate processes (or always blocks) is a bad idea and will result in a multi-driver error in the tools.
However, one of my acquaintances claims that if the …
- 5,412
1
vote
Accepted
Modelling current to remain in particular range for fixed simulation time
I would use a random number generator to generate a random number and then assign it to a state based on its value.
For example, if I generate a random number between 1 and 100, then if it's below 7 …
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7
votes
0
votes
1
answer
275
views
Is the simulated clock cycle latency through an entity accurate?
If I write an entity that takes 10 clock cycles to produce output from input, is it safe to assume that this is the case when implemented in hw, or are there other factors to consider?
Does the simu …
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3
votes
3
answers
811
views
32-way Mux Produces Horrible Timing Problems
I'm coding a 32 way mux in verilog.
The input is a counter which counts from 0 to 31, incrementing each clock cycle. Each counter value selects a different slice of a vector as an output. …
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3
votes
Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock
All you need to do is paste it into your verilog file.
// Instantiate the module
DCM32to50 instance_name (
.CLKIN_IN(CLKIN_IN),
.CLKFX_OUT(CLKFX_OUT),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), …
- 5,412
2
votes
How to Implement this special selector?
To elaborate on why high impedance isn't a condition that can be checked for:
When a signal is high impedance, the FPGA just leaves that signal floating. Usually if you drive a signal to 0, it will c …
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5
votes
Accepted
Please explain the following integer constant used in verilog
This is shown here:
16'd5
The decimal 5 only needs 3 bits (101), however, this value may be desgnated for a 16 bit bus:
wire [15:0] test;
assign test = 16'd5;
While verilog does pad smaller sizes, …
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2
votes
How to give a 2-D array as output of a function in Verilog?
For example, say x is the 32 bit address and y is 128 bit address,
square[x][y] maps to flat[x + y << 32]
To work this out in verilog, you can loop through x and y in a nested fashion, and your new …
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