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Results tagged with synthesis
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user 169836
Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.
4
votes
VHDL optimization
Synthesis tools are very, very good at optimizing.
As to "speed" versus "area": every synthesis tool I know has settings where you can choose which one you prefer. … The only time your gates are not "moved around" is if you explicitly tell the synthesis tool to not do that. …
- 14.6k
0
votes
vhdl synthesizable code
I am not going to write the whole code but this may help.
Below is a code snippet which detects rising and falling edges. But it is fully synchronous. Beware that the code assumes input4 is synchrono …
- 14.6k
3
votes
Transfer Verilog Code to For Loops Syntax
Ok, a bit longer answer:
For loops are perfectly fine for synthesis. Anybody who tells you different is absolutely wrong.
As Tom Carpenter says: the loop has to be deterministic. …
- 14.6k
0
votes
question about Vivado synthesis and implementation
You can, with some effort, make the synthesis tool leave your constants alone. But I think it is a bad idea:
You run the risk that the number of I/O ports exceeds your chip pin count. … On some tools synthesis might still work but Place & Route will not.
The logic will not be the same compared to when you add the real code to set the input signals and access the result. …
- 14.6k
1
vote
Synthesis Result : RTL vs Technology Map Viewer
The Logic mapper uses "functional" symbols, which is just a square with what function that block fulfills. This can map onto all kinds of logic.
For example if you use a '+' the function will be 'add …
- 14.6k
0
votes
Accepted
How does synthesis tool handle the ports either driven by or to a module that is empty(Black...
If you define the module as 'black box' the synthesis stool will not optimize it away or use it to optimize signals away. …
- 14.6k
4
votes
Accepted
What is the purpose of this Verilog code for implementing 3-port Block RAM?
This has been unanswered for a day and I think I know why. If Verilog code becomes a bit bigger and complex it is very difficult to see all the temporal relations.
Even if the user puts lots of comme …
- 14.6k