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Results tagged with vlsi
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user 237839
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
2
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58
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Why does the body effect result in these \$V_{OH}\$ and \$V_{OL}\$ values?
Consider the following circuit and discussion which come from my textbook (Brown and Varnesic Fundamentals of Digital Logic):
Of course, the exercise is to notice that NMOS and PMOS are very bad in a …
- 1,219
3
votes
1
answer
379
views
How does this logic gate naming convention work?
In their CMOS VLSI Design, Weste and Harris seem to use a naming convention for logic gates which I cannot quite seem to define in my head. …
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1
vote
1
answer
97
views
What does ‘full custom’ really mean?
It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. …
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0
votes
1
answer
53
views
What does optimizing fabs "for throughput rather than latency" mean?
In the context of a whirlwind tour of the modern VLSI design, tapeout, and fabrication flow in their CMOS VLSI Design, Weste and Harris write the following:
Multiple chips are manufactured simultaneously …
- 1,219
0
votes
1
answer
150
views
Why doesn't body effect place limit on number of series transistors in CMOS network?
My textbook (Weste and Harris) asks the following:
Does the body effect of a process limit the number of transistors that can be placed in series in a CMOS gate at low frequencies?
It answers with t …
- 1,219
2
votes
2
answers
251
views
On different well processes (reasons)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the difference between n-well, twin-well, and triple-well processes. …
- 1,219
0
votes
On different well processes (reasons)
Some of this is answered in Chapter 2.6 of Baker's CMOS Circuit Design, Layout, and Simulation:
a) He argues that a big reason for using twin-well even if you can't isolate the p-wells from one anothe …
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1
vote
2
answers
188
views
Is there any problem with implementing a tristate buffer this way?
Consider the following implementation of an inverting tristate buffer in CMOS:
My textbook (Weste and Harris's CMOS VLSI Design) says that to implement a (noninverting) tristate buffer we should precede …
- 1,219
0
votes
Accepted
Why doesn't body effect place limit on number of series transistors in CMOS network?
I think my problem was with not understanding what was meant by "limit" in the problem statement.
In terms of the setup of the problem, we are to imagine the setup for the problem as that we have a se …
- 1,219
0
votes
2
answers
112
views
Why do we need output isolation for power-gated blocks?
In their CMOS VLSI Design, Weste and Harris give the following discussion of power gating a block of logic:
I am in particular interested in understanding the need for output isolation here. …
- 1,219
1
vote
1
answer
184
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On DC transfer characteristics, logic levels, and the static discipline
One thing that's confused me ever since I started studying digital design is what it means when books say, roughly, that we can choose or define the input and output thresholds for a given circuit fam …
- 1,219
0
votes
1
answer
197
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Why do two nonoverlapping phase completely obviate the possibility of hold time issues?
In Weste and Harris's CMOS VLSI Design, they write
In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop triggers …
- 1,219
2
votes
2
answers
652
views
Why do we alternate directions between metal layers?
In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that
Another important decision during floorplanning is to …
- 1,219
1
vote
2
answers
75
views
How does MOSIS let designers “share” a mask set?
In Weste and Harris's CMOS VLSI Design, they describe MOSIS as follows:
The MOSIS service [Piña02] is a low-cost prototyping service that collects designs from academic, commercial, and government customers …
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0
votes
0
answers
22
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Does minimizing stages necessarily give best outcome when designing circuit under a delay co...
In the context of digital design, a common situation is to have to design a circuit for minimum energy under a delay constraint. Suppose a given circuit can be implemented with various stages. Is it n …
- 1,219