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Results tagged with adc
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user 262297
An ADC is an Analog to Digital Converter. This device converts analog signals into digital form. It is mainly used by digital circuitry to take analog measurements.
2
votes
1
answer
522
views
How to remove gain and offset errors from ADC logic?
I have a 3-bit converter with ideal LSB of 50 mV. The following table shows the non-ideal logical values.
I need to remove gain and offset errors from the codes below.
I read on the internet that one …
- 1
7
votes
4
answers
2k
views
Why does quantization noise in ADC have such a wide bandwidth?
In the slide shown below by red arrow we have quantization noise up to fs/2, but why?
From Nyquist fs=fb/2 for good sampling but why is there noise here noise up to fs/2?
What is the logic ?
- 1
0
votes
1
answer
87
views
why SAR ADC charge sign is negative
In the formula shown bellow why the charge between V+ and GND is minus to the charge of Vref and V+ ?
Thanks.
- 1
0
votes
0
answers
125
views
SAR ADC offset calculation
In the photo shown bellow we have a calculation for SAR ADC voltage NODE sighned as Vout. …
- 1
2
votes
3
answers
938
views
Visualising redundancy in a 1.5 bit pipeline ADC
In a pipeline ADC, we have redundancy where we increase number of levels to somehow more accurately measure the input and reduce the error. …
- 1
0
votes
0
answers
47
views
What is INL and DNL value for this case
i am trying to recreate the calculation for INL and DNL
for n=100
$$S_{avg}=0.091$$
$$INL=\frac{(V_{actual}-V_{uniform})}{S_{avg}}=\frac{(0.33-0.35)}{0.091}=-0.21$$
$$DNL=\frac{(V_{actual_{100}}-V_{ac …
- 1
0
votes
0
answers
118
views
Why INL is not a sum of previos DNL
In the ADC I have 2 bit system and Vref=1V with actual voltage shown as shown bellow.
I have transformed the actual into UNIFORM as shown bellow and i produced INL from it. …
- 1
0
votes
1
answer
74
views
Why is the timing diagram of combined SAR ADC more efficient?
In the timing diagram below we have one SAR sampling while the other is proccesing.
If we have a stream of samples which is twice as fast then the rate of each SAR, given data stream of N+1,N,N-1,N-2 …
- 1
0
votes
2
answers
309
views
What is full scale of flash ADC?
My input signal is a sine of amplitude 1 so the input ranges from -1 to 1 so the range is 2 (pk-pk.)
On the other hand, the flash voltage divider ladder goes from 0 to Vref.
Which one of the two optio …
- 1