Skip to main content
Search type Search syntax
Tags [tag]
Exact "words here"
Author user:1234
user:me (yours)
Score score:3 (3+)
score:0 (none)
Answers answers:3 (3+)
answers:0 (none)
isaccepted:yes
hasaccepted:no
inquestion:1234
Views views:250
Code code:"if (foo != bar)"
Sections title:apples
body:"apples oranges"
URL url:"*.example.com"
Saves in:saves
Status closed:yes
duplicate:no
migrated:no
wiki:no
Types is:question
is:answer
Exclude -[tag]
-apples
For more details on advanced search visit our help page
Results tagged with
Search options not deleted user 311028

A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".

0 votes
1 answer
599 views

What are the possible strategies to transfer data from an FPGA accelerator to a hard-core CPU? [closed]

My question is: what is the best/simplest strategy to transfer data from the FPGA to the CPU? … Note the following: I am using a Zynq UltraScale+ MPSoC from Xilinx (more precisely the zu3eg), and CPU and FPGA are on the same physical chip. …
leopicchio's user avatar
2 votes
1 answer
368 views

VERILOG: why Xilinx AXI Slave declares all output signal as a wires and not reg?

It seems to me that this would simplify the code and the actual implementation in the FPGA... is there any particular reason why they chose to do so? Thanks a lot for your help!!! …
leopicchio's user avatar