Search Results
| Search type | Search syntax |
|---|---|
| Tags | [tag] |
| Exact | "words here" |
| Author |
user:1234 user:me (yours) |
| Score |
score:3 (3+) score:0 (none) |
| Answers |
answers:3 (3+) answers:0 (none) isaccepted:yes hasaccepted:no inquestion:1234 |
| Views | views:250 |
| Code | code:"if (foo != bar)" |
| Sections |
title:apples body:"apples oranges" |
| URL | url:"*.example.com" |
| Saves | in:saves |
| Status |
closed:yes duplicate:no migrated:no wiki:no |
| Types |
is:question is:answer |
| Exclude |
-[tag] -apples |
| For more details on advanced search visit our help page | |
Results tagged with digital-logic
Search options not deleted
user 35762
Digital electronics treats discrete signals, unlike analog electronics which treats continuous signals. Digital logic is used to perform arithmetic operations with electric signals and constitutes the base for building CPUs.
0
votes
2
answers
998
views
Limitations of using minimum no. of MUXes for a given boolean function
Given a specific Boolean function, is there any restriction on the minimum no. of multiplexers required to implement that function? Is there any theory on that?
- 666
4
votes
2
answers
45k
views
Subtraction using adder circuit
I need some really basic help here. Can I use a 4bit adder chip as a subtracter by using the 2's complement for the number to be subtracted?
- 666
0
votes
1
answer
950
views
Connecting multipliers to increase operation bit width
I successfully created a 2 bit digital multiplier. Can I use that 2 bit multiplier to create a 4 bit multiplier and then use that to create an 8 bit multiplier and so on? What I basically mean to ask …
- 666
0
votes
1
answer
198
views
Adder hardware logic
simulate this circuit – Schematic created using CircuitLab
If this circuit is a part of a 4 bit full adder, where A1,B1 are adder inputs and C1 is carry in from previous bit, does C2 give the c …
- 666
0
votes
2
answers
1k
views
design data storage using a simple MUX instead of a complicated SR latch
I was studying sequential circuits and I am at the very infant stages of the course. After studying the D flipflop I realized that the purpose was to let the data line change the output if clk=1 or ke …
- 666
1
vote
NAND and NOR logic gates
for NAND gate implementation...
simulate this circuit – Schematic created using CircuitLab
for NOR gate implementation
simulate this circuit
- 666
2
votes
Accepted
Odd Parity Output as Input to Second Circuit
As far as I know, the first circuit is basically 2 cascaded XOR gates which outputs 1 if the the no of high inputs are odd. Hence circuit 1 outputs 1 when odd parity is satisfied. If you want circuit …
- 666
0
votes
Is D flip flop can be combination circuit?
The equation for a D flip flop is Q(n+1)=D.C+Q(n).C'.
This means that when Clock is 1, the data is written to the output, but when clock is zero, the data is in read mode and cannot be written. The Q …
- 666
0
votes
2
answers
597
views
Use of Toggle flip-flops and JK flip flops
I was studying digital electronics, especially latches and flip-flops and the like and I came to understand that flip-flops are basically memory storage elements, in that case why would I need configu …
- 666
0
votes
1
answer
208
views
Using capacitive coupling to implement pulse transition
I was reading about master-slave flip flops, used to implement edge triggering and I read that instead of using master slave configurations, using RC coupling to clock inputs could also enable pulse t …
- 666
1
vote
3
answers
1k
views
Need for edge triggered versions other than master slave
I am studying synchronous digital circuits and I have come to the conclusion that master slave flip flops are edge triggered? Is my study correct? If master slave versions ARE edge triggered, why do w …
- 666
0
votes
AND, OR gates: 3 transistors. NAND, NOR gates: 2 transistors. Why?
simulate this circuit – Schematic created using CircuitLab
I have drawn the approximate circuits for you. Please do the math.
- 666