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Results tagged with synthesis
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user 39019
Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.
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How can I specify "don't care" signals in VHDL?
I will leave it to an LRM expert to provide a more detailed answer, but in short, your approach should be valid - I ran a quick test with a recent version of Quartus, and it handles '-' like it's supp …
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