Search Results
| Search type | Search syntax |
|---|---|
| Tags | [tag] |
| Exact | "words here" |
| Author |
user:1234 user:me (yours) |
| Score |
score:3 (3+) score:0 (none) |
| Answers |
answers:3 (3+) answers:0 (none) isaccepted:yes hasaccepted:no inquestion:1234 |
| Views | views:250 |
| Code | code:"if (foo != bar)" |
| Sections |
title:apples body:"apples oranges" |
| URL | url:"*.example.com" |
| Saves | in:saves |
| Status |
closed:yes duplicate:no migrated:no wiki:no |
| Types |
is:question is:answer |
| Exclude |
-[tag] -apples |
| For more details on advanced search visit our help page | |
Results tagged with verilog
Search options not deleted
user 459627
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
1
vote
1
answer
29
views
Verilog - problem reading giving wrong value at interconnected bus
I have the task of designing an 8x8 bit memory in Verilog using CMOS. (orginally asked at Verilog - 8x8 memory unit - wrong value read, but asked to provide more details). … input valid,
input[2:0] addr,
output[7:0] sel
);
wire addr_NOT[2:0];
// Generate NOT addresses
not(addr_NOT[0], addr[0]);
not(addr_NOT[1], addr[1]);
not(addr_NOT[2], addr[2]);
// nb - verilog …
- 35
0
votes
Memory module with SR-Latch - value overritten when writing to another cell
The problem appeared to be caused by some problems with the SR latch.
After adding a little delay on one of the NOR-gates, it seems to work perfectly.
Fix is the #1 in:
nor #1 latch_upper(Q, Q_not, R) …
- 35
1
vote
2
answers
46
views
Memory module with SR-Latch - value overritten when writing to another cell
I have created an 8x8 memory module.
Currently, I have the following:
Bitcell - takes in signals sel (if its selected), rw (read = 0, write = 1) and input. If sel=0, output is high impedance. If sel= …
- 35
1
vote
1
answer
15
views
Verilog - 8x8 memory unit - wrong value read
I have the task of designing a 8x8 bit memory in Verilog using CMOS.
Currently, I have the following:
Bitcell - takes in signals sel (if its selected), rw (read = 0, write = 1) and input. …
- 35