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Results tagged with state-machines
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user 6334
A finite state machine (or state machine) is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.
2
votes
Finite state machine inputs
Yes, there are 32 possible input combinations for each state. But in some states, some of the inputs might be "don't cares", so you won't have to write out all the combinations explicitly, whether you …
- 134k
1
vote
Moore machine state diagram and state table
the output only depends on the current state Then why does the table for states F and H say the output is independent of the input?
Because if it depends only on the current state, then it can't …
- 134k
1
vote
Moore machine for LED display
State machines have an input that by convention isn't explicitly mentioned on the state diagram: the clock. In your case, it appears that what you call "the toggle button" is used to generate the cloc …
- 134k
5
votes
Next-State Tables
You start with the basic form:
Inputs | Outputs
------------------
|
Then you figure out what your inputs and your outputs are. In this case, your inputs are just the current state, and t …
- 134k
0
votes
Accepted
Can FSMs be Timed and Recursive?
Timed and recursive state machines are much more common than untimed state machines, at least among state machines that are deliberately designed as state machines rather than circuits designed by som …
- 134k
0
votes
How to set initial state of 4 bit "exclusive output" Latch?
In the given circuit, the capacitor should work in most cases to bring the circuit up in the expected state.
But this could be defeated, for example by ramping Vdd up very slowly during power up. The …
- 134k
1
vote
Can someone help me complete this Verilog code for this sequential circuit?
Your state diagram looks good.
Your state transition table looks fine.
Your Verilog is not at all right. It's so far from right, it's hard to know where to begin fixing it.
In my experience, the b …
- 134k
1
vote
Verilog- Why is my state machine output arriving one clock cycle earlier?
Check this code carefully:
s2: begin
if (timer >= 50550) begin //here read input
state<=s3;
end
else state<=s2;
end
I see a few potential issues:
This waits for 50,000 clock …
- 134k