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Results tagged with verilog
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user 6780
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
2
votes
I am not able to instantiate sub modules inside always block
You can't instantiate modules in always block. Do it before and assign a clock to that module.
- 1,031
2
votes
Taking output from FIFO implemented in verilog
Two options:
Either You need 23 times faster clock and read the data with that clock.
Read FIFO using the same sequential reading method, but burst all the data to output after the data is read. Thi …
- 1,031
1
vote
Stress testing an FPGA's power supply
Also remember, that FPGA itself is not the only one power eater. E.g. DDR3 RAM combination of 16GB can eat a burst of >5A in some cases.
- 1,031
4
votes
Merge a differential pair into one signal
Altera FPGAs can easily interface LVDS signals. Assign a signal to a pin in Pin Planner, then select that pin type as LVDS and a complementary pair will be generated automatically. Plus it will also a …
- 1,031
2
votes
View more than 100 worst-case paths in Quartus II
Go to TimeQuest, generate required reports (I like using Report all summaries macro), select failing report, select failing path clock, right-click -> Report Timing..., Report number of paths: enter a …
- 1,031
3
votes
Accepted
My design is not meeting timing. What can I do?
Run design assistant and try to optimize design for speed if Your timing constrains doesn't help You to reach the required times. What frequency do You need and how much do You get? What's the worst p …
- 1,031
4
votes
Accepted
How to generate wait until division is over in verilog?
Create a state machine where it will be stuck in a particular state until done signal asserts.
- 1,031