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Results tagged with digital-logic
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user 72936
Digital electronics treats discrete signals, unlike analog electronics which treats continuous signals. Digital logic is used to perform arithmetic operations with electric signals and constitutes the base for building CPUs.
3
votes
0110 moore overlapping in verilog
The problem is that your input x is asynchronous to the clock. You must synchronize it to the clock by driving it in the testbench the same way your design synchronizes to the clock.
Your testbench c …
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1
vote
Accepted
What's wrong with my Verilog code
Verilog module names must not begin with a number. Change:
2Assignment
to something like:
Assignment2
Make this change to both files.
The same applies to other Verilog identifiers, such as signal n …
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3
votes
Why is the value of product (y) unknown?
When I run the simulation on EDA Playground, the Aldec simulator you selected generates several warning messages:
# SLP: Warning: testbench.sv (9): Length of connection (16) does not match the length …
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3
votes
Accepted
Verilog code for solving a logic gate has this error: Invalid module instantiation
The problem is with the connections to the module instance. You connected a reg to the module output: B in the main module is connected to C in the Exercise module.
You are using connection by order, …
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4
votes
Accepted
Which of the following PRBS generator algorithms is favored practice and why?
Your 5 code examples do not adhere to good Verilog coding practices. For example, the 1st example uses both blocking and nonblocking assignments inside the same always block. Generally, it is better …
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4
votes
LED to the carry out pin of my 7483 IC doesn't glow in Proteus
This data sheet for a similar IC shows pin C0 as an input ("Carry Input"), and pin C4 as an output ("Carry Output"). From your diagram, it looks like you have them swapped. Be sure to check whatever …
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6
votes
Is the Gray code unique?
According to Wikipedia:
In principle, there can be more than one such code for a given word
length, but the term Gray code was first applied to a particular
binary code for non-negative integers, the …
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1
vote
Accepted
AT25SF081 FLASH device Status register CS
You should also consult Figure 13-1 Serial input timing. That figure shows the clock (SCK) as free-running, which means that it is toggling both when CS is high and low. This is one operating mode o …
- 9,763
1
vote
Accepted
Verilog - 8x8 memory unit - wrong value read
Any ideas?
Yes, there are plenty of ideas.
Since your simulation log indicates there are problems with outp, you need to focus your debug efforts there.
Just by inspection, this code looks suspiciou …
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4
votes
How to define a function in Verilog?
The compile error is telling you that Verilog does not allow you to declare a signal using a variable number of bits. You are trying to declare W with a variable number of bits (k is a variable), whi …
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1
vote
generate-for loop in Verilog
The purpose of generate for loops is to create a constant number of hardware logic items. sel is fine because it is a constant value because you declared it with a parameter and gave it a numeric val …
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1
vote
Accepted
Verilog - problem reading giving wrong value at interconnected bus
the write operations work successfully
There is insufficient evidence of that in your question. Instead of relying solely on the information in your simulation log file, you should also dump wavefo …
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3
votes
Unexpected behaviour from an apparently simple Verilog memory implementation
I can not reproduce your result exactly. When I try to compile your code with iverilog, I get syntax errors, and I can not run a simulation. You and I are probably using different versions of iveril …
- 9,763
1
vote
Memory module with SR-Latch - value overritten when writing to another cell
The fundamental problem is that you have been lead down the wrong path with your approach to Verilog modeling. You should always write Verilog code at the highest level of abstraction. You are tryin …
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1
vote
Accepted
What happens in Verilog when I assign the value of a button to a register with a non blockin...
"value" is scheduled to be 1 at the end of the current clock cycle
That is incorrect. You misunderstood the meaning of nonblocking assignments. value is scheduled to be 1 at the end of the current …
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