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Results tagged with digital-logic
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user 72936
Digital electronics treats discrete signals, unlike analog electronics which treats continuous signals. Digital logic is used to perform arithmetic operations with electric signals and constitutes the base for building CPUs.
1
vote
Accepted
What happens in Verilog when I assign the value of a button to a register with a non blockin...
"value" is scheduled to be 1 at the end of the current clock cycle
That is incorrect. You misunderstood the meaning of nonblocking assignments. value is scheduled to be 1 at the end of the current …
- 9,763
1
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Memory module with SR-Latch - value overritten when writing to another cell
The fundamental problem is that you have been lead down the wrong path with your approach to Verilog modeling. You should always write Verilog code at the highest level of abstraction. You are tryin …
- 9,763
1
vote
Accepted
Verilog - problem reading giving wrong value at interconnected bus
the write operations work successfully
There is insufficient evidence of that in your question. Instead of relying solely on the information in your simulation log file, you should also dump wavefo …
- 9,763
1
vote
Accepted
Verilog - 8x8 memory unit - wrong value read
Any ideas?
Yes, there are plenty of ideas.
Since your simulation log indicates there are problems with outp, you need to focus your debug efforts there.
Just by inspection, this code looks suspiciou …
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2
votes
Accepted
Latch inference using assign statement in Verilog
Th original question showed this code:
wire output;
assign output = (count > 3) ? 1'b1 : (count == 7) ? 1'b0 : count;
There are a few issues with the Verilog code.
There is a syntax error becau …
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1
vote
generate-for loop in Verilog
The purpose of generate for loops is to create a constant number of hardware logic items. sel is fine because it is a constant value because you declared it with a parameter and gave it a numeric val …
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3
votes
Unexpected behaviour from an apparently simple Verilog memory implementation
I can not reproduce your result exactly. When I try to compile your code with iverilog, I get syntax errors, and I can not run a simulation. You and I are probably using different versions of iveril …
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1
vote
Accepted
Bidirectional Pin Handling In Verilog
if the mode is OUTPUT, I want to assign 7 to the bidirectional pin
The following code is incorrect:
assign data = (mode == OUTPUT) ? 32'dz : 32'd7;
You need to swap the order of the assignments to …
- 9,763
4
votes
Usage of edge-triggering constructs in Verilog
It is not a good design practice because there could be glitches on trigger0. trigger0 is a combinational decode of several bits which will have slightly different delays from each other when synthes …
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4
votes
Help to solve 74LS85 comparator
As the datasheet specifies, A is a 4-bit number where A3 is the MSB and A0 is the LSB. Starting from the left of the timing diagram, ignore the section where all A signals are red. In the 1st square …
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2
votes
What to watch out for in combinatorial logic in reset value?
Aside from the excellent advice in the other answer, here are some other considerations regarding this line of code:
byte data;
Things to keep in mind is that the byte data type is:
Signed
2-state
…
- 9,763
1
vote
Accepted
AT25SF081 SPI Flash to 12MHz FPGA signal testbench
In the main module, you declared the led output signal, but you did not drive the signal. In other words, led is not connected to a driver. This is why led is not being set to a known value (it has …
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1
vote
Accepted
AT25SF081 SPI Flash to 12MHz FPGA signal timing
data on the SI line should be sampled by the flash device at least 2
nanoseconds after it is clocked out
No. The figure 13-1 waveform means that your FPGA must assure that the SI line is stable at …
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1
vote
Accepted
AT25SF081 SPI Flash device terminology
It is necessary to meet the timing requirements on the AT25SF081 device. For the SI data input pin, refer to Figure 13-1. Serial Input Timing, where it shows that the SI input pin is sampled on the …
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1
vote
Accepted
AT25SF081 FLASH device Status register SI SO transition
Figure 10-1 merely shows you the bit order. The figure does not have enough detail to show the timing requirements. You need to view it in conjunction with the timing information elsewhere in the da …
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