Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange
Search type Search syntax
Tags [tag]
Exact "words here"
Author user:1234
user:me (yours)
Score score:3 (3+)
score:0 (none)
Answers answers:3 (3+)
answers:0 (none)
isaccepted:yes
hasaccepted:no
inquestion:1234
Views views:250
Sections title:apples
body:"apples oranges"
URL url:"*.example.com"
Favorites infavorites:mine
infavorites:1234
Status closed:yes
duplicate:no
migrated:no
wiki:no
Types is:question
is:answer
Exclude -[tag]
-apples
For more details on advanced search visit our help page
Results tagged with Search options user 103137

A digital circuit that literally "counts" - it progresses through a sequence of states that are representative of some value. It need not count in a natural progression i.e. 1,2,3,4,5 etc. to be considered a counter (i.e. you can have different count sequences) each count value need not be of significance to other circuits (i.e. sometime it's sufficient that the counter counts to some value and then stops). Examples are Gray code, up/down counter.

0
votes
1answer
I'm trying to implement a synchronous up-down counter in verilog with the following rules: Counter only changes on rising edge of clock When reset=1, count goes to 00, normal operation when reset … counting up, does NOT go from 11 to 00 (i.e. stays at 11) So far my code is: module counter ( input clock, input reset, input en, input …
asked Apr 1 '16 by tlb
1
vote
1answer
After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops. Here's the D Flip Flop code (which was tested and works … And my Down Counter Code using this image: module Count4Down ( input wire reset_n, input wire clk, output [3:0] q ); wire qn0, qn1, qn2, qn3; DFlipFlop ff0(reset_n, clk …
asked Mar 22 '16 by tlb