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Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

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You can get Quartus to generate a TCL file (click "Project → Generate TCL file for Project...") that will set up your project from scratch, including any generated IP you're using. So ultimately, all … you need to save is that script, the Quartus Project File (.qpf) and all of your HDL source files. Building from a fresh clone is more than a single step, however: Open the project (the .qpf file) execute the setup script ("source" the .tcl file) click "Compile" …
answered Apr 3 by Dave Tweed
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By just typing "quartus fpga manual placement" into Google, I found this Application Note. While it talks about placing PLLs specifically, it seems to show the general technique for placing any …
answered Feb 29 '16 by Dave Tweed
2
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The fundamental problem is that you have conditional statements like if rising_edge(...) then buried inside a process that is already conditional on a clock edge. You can't have multiple edge sensi …
answered Dec 30 '16 by Dave Tweed
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Generally speaking FPGA synthesis tools do not let you use logic to generate an internal clock without requiring you to explicitly run it through a clock buffer. You may also have to declare the net a …
answered Mar 12 '16 by Dave Tweed
6
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A divider is a series of subtractions and multiplexers that select the value for the next step. If it is done purely combinatorially, then the critical path through all of this logic is quite long (ev …
answered Mar 27 '14 by Dave Tweed
3
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The Quartus toolset (and FPGA tools in general) are intended for synchronous design. Trying to use them to develop a purely asynchronous design requires a great deal of experience, and is still often …
answered Aug 26 '18 by Dave Tweed
0
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The you need to convince the synthesizer that a and b can change at any time — if it believes that they are constants, it will optimize them away. It doesn't matter how they can change. One simple wa …
answered Mar 4 '16 by Dave Tweed
0
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You can't make assignments to a signal (such as rf[]) in more than one always block.
answered Oct 27 '18 by Dave Tweed
4
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Yes, there is "bouncing" — but in this context, we call them "glitches". The comparator (count > 26'd24999999) represents a rather large amount of combinatorial logic, and there's no chance that all p …
answered yesterday by Dave Tweed