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A circuit that converts a signal from one form to another. Analog to digital, Digital to analog, Voltage to current, Current to voltage etc. The key to understanding is the transformational properties of the circuit as opposed to just amplification or buffering.

Batteries often have capacities of >> 10k Farads and on cars will demand full current which can burn out Alternator diode bridges if undercharged completely and results in currents > 100A for brief pe …
answered Sep 19 '16 by Sunnyskyguy EE75
This is the F/V gain 100Hz/V for (1-1k)/10V. and 24Hz/V for 10 to 250 Hz / 10V. Implementation would be done uC with counter timers for integration of. f or duty cycle and DAC signal conditioner ga …
answered Sep 12 '18 by Sunnyskyguy EE75
For 9V in and 400Vout using R3=10M with divider of 20k pot +R4=22k to FB feedback.You need 400 to 100 gain change so pot changes to 4x(20+22) 168k. = 250k pot // with a shunt R = 500K Then no change …
answered Dec 17 '17 by Sunnyskyguy EE75
when DC In is removed, the bulk storage cap is the reservoir to attempt to boost the decaying output. Your use of PG is unclear for Reset and this ought to be used to disable EN as per your requireme …
answered Jul 5 by Sunnyskyguy EE75
Plan B Analysis Since Tx on RS232 is idle at -V -5V ~ -15Vtyp and then clamped and rectified to -6V by zener. So -Vcc is always there with the 10kHz charge pump creating +Vcc. It might get weaker wi …
answered Sep 17 '18 by Sunnyskyguy EE75
The negative sync tip is easily done using AC coupling using an active clamp circuit during the sync positive edge with a 1 shot to short the output during the back porch. Although your is DC coupled …
answered Feb 14 '18 by Sunnyskyguy EE75
It can cause communication issues if one side is earth grounded with an EMI filter to ground and the other has a loop antenna for cabling on a floating supply without earth grounding. Even with diffe …
answered May 24 by Sunnyskyguy EE75
while L feeds continuous current to supply the load. In real life it is a discontinuous Boost converter that can be much greater than 2*E or just the same as E depending on the proper choices of components to supply the load. ( minus diode drops) …
answered Oct 3 '16 by Sunnyskyguy EE75
This simple regulator demands that both input and output cap are low ESR for low ripple out. This means ESR*C < 20us. This breakpoint effectively attenuates the ripple but also reduces the AC feedb …
answered Aug 28 '17 by Sunnyskyguy EE75
One solution is: binary detect with hysteresis, MUX and use a PISO register (Parallel In Serial Out), detect sensor in software and decode events or detect single events in hardware then clear when …
answered Jan 16 by Sunnyskyguy EE75
SEARCH for TACH designs. This is very common. But define your specs carefully; f1 min.=___ Hz Vout=___ % Ripple=___ f2 max.=___ Hz Vout=___ Slew rate=____ ms or ___ cycles ( f1 to f2 t …
answered Apr 18 by Sunnyskyguy EE75
I would provide a source storage cap impedance based on <1% of the step load Z. For low ESR ceramic cap for the step load transition edge using Zc(f) for f=1/3tr Then for ripple current using RC= 10 …
answered Oct 31 '16 by Sunnyskyguy EE75
converter, ( transformer + rectifier with optical feedback isolation) perhaps the most common reliable low cost type with similar topology used in many ATX PSU's . …
answered Oct 15 '16 by Sunnyskyguy EE75
When you copy an EDN design and make major substitutions with disregard to voltage and current swing , without reason, you get numerous faults. Get the right parts or get back to Basics On the curren …
answered Mar 20 '18 by Sunnyskyguy EE75
Since excitation current depends on V/f ratio and inductive impedance, you must consider the 60/50 ratio of higher excitation current of running it at 50 Hz when trying to match the 120V 60Hz rating f …
answered Jan 18 by Sunnyskyguy EE75

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