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A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices), formerly Altera.

1
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The FPGA does not have internal flash memory, just SRAM. Instead, it loads the configuration from an external flash chip after reset. Typical Altera developer boards have two programming headers, one …
answered Jan 26 '16 by Simon Richter
1
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Unless you constrain that path, there will be no guarantee on timing, so knowing this number wouldn't solve your problem. AN433 has a few examples that may be relevant to what you want to do.
answered Sep 23 '18 by Simon Richter
0
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I'd try only with those devices that have a hard IP block for dynamic PLL reconfiguration unless the input clock has a narrow frequency range. A PLL that expects to generate 10 MHz from 10 MHz will p …
answered Jun 19 by Simon Richter
2
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There is no way to read back the current configuration. If your development board is wired for JTAG mode, as it looks like from your screenshot, then simply writing a new configuration will update th …
answered Jun 8 '15 by Simon Richter
1
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That ID is from the FPGA itself, and hardcoded, it is used to verify that the FPGA model is exactly as configured because a bitstream for a different model might damage the FPGA (e.g. by trying to dri …
answered May 20 by Simon Richter
2
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The clock would be connected on the board to a pin you can use as a clock input. To understand what you are doing, I'd start with a simple project and then improve that. The first implementation wou …
answered Apr 28 '15 by Simon Richter
1
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For differential inputs it is sufficient to create a mapping for the port to the positive pin of the pair, specifying a differential I/O standard. This automatically creates a second mapping for the n …
answered Jun 19 by Simon Richter
2
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1answer
I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says that fixedclk_serdes may not be deri …
asked Oct 15 '15 by Simon Richter
3
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Honestly: it does not matter much. Both companies are about on par with features: lots of lookup tables, some dedicated blocks like multipliers or I/O), development environment (annoying) pricing ( …
answered May 6 '16 by Simon Richter