Search type Search syntax
Tags [tag]
Exact "words here"
Author user:1234
user:me (yours)
Score score:3 (3+)
score:0 (none)
Answers answers:3 (3+)
answers:0 (none)
isaccepted:yes
hasaccepted:no
inquestion:1234
Views views:250
Sections title:apples
body:"apples oranges"
URL url:"*.example.com"
Favorites infavorites:mine
infavorites:1234
Status closed:yes
duplicate:no
migrated:no
wiki:no
Types is:question
is:answer
Exclude -[tag]
-apples
For more details on advanced search visit our help page
Results tagged with Search options answers only user 6334

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

1
vote
As the other answers say, your problem is declaring x and out as register type. When you assign to something in an assign statement, or by connecting it to an output port of a module instance, you n …
answered Feb 8 '16 by The Photon
1
vote
The problem is not in your synthesizable module, it's in your testbench. So it's no wonder Quartus didn't catch it --- Quartus will only be trying to compile the actual function module, Cam. You …
answered Sep 15 '18 by The Photon
0
votes
From comments: I almost get what i wanted link i needed dout loaded WITH posedge sclk_adc You can just update dout on the edge of sclk_adc: always @(posedge sclk_adc) begin dout <= shi …
answered Jul 25 '18 by The Photon
0
votes
Comparators are relatively complex logic, with long carry chains. I'd recommend something like this: module downClockerTest(pulse, clk, reset); output reg pulse; reg [24:0] count; inpu …
answered 2 days ago by The Photon
5
votes
I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams). Because your multiplying coefficients are all powers of 2, your multiplies can a …
answered Jul 26 '17 by The Photon