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Xilinx Integrated Software Environment (ISE) is a suite of design and analysis software for their range of CPLD and FPGA devices.

3
votes
path is only 8 levels deep. This is part of your problem, not only the propagation delays are enormous from going trough so many LUTs, ISE has a lot of problem routing the design in an efficient way … are registered (since they come from the output of another module). Another part of your problem is these combinational loops that ISE report. Those are likely to change or even disappear once you redesign to add pipeline registers, but you shouldn't even try a bitstream with these in it. …
answered Apr 6 '15 by Jonathan Drolet
3
votes
First of, I disclaim that I never used the Xilinx CORDIC core, but I know Xilinx and I know CORDIC... Also, I invite you to check out Wikipedia to have a better understanding of what the core do. The …
answered May 21 '15 by Jonathan Drolet
6
votes
My personal workflow (I mention planAhead, but vivado is similar), with goal to add as little as possible to source-control: Files exist outside the planAhead project directory. Take care since if y …
answered Apr 8 '15 by Jonathan Drolet
3
votes
Xilinx has been inconsistent with the LVDS iostandard, I won't delve into earlier generations than spartan-6! First, LVDS is current based (3.5mA into 100 ohm, around 350mV swing) and is electrically …
answered Mar 18 '15 by Jonathan Drolet