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Despite the name, it is unrelated to the bidirectional I²C bus. I²S is a media-specific protocol which uses at least three signals: Bit CLK, Word CLK, and at least one data line.

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I'm doing a sound analyzing project on the Zybo board and I'm having hard time using the AXI DMA for transferring data from the I2S controller to RAM. I'm using the I2S controller from the Digilent's … ) and there's also the possibility of direct register access. The Zybo base system example uses the latter. The I2S IP uses a 8x24 FIFO for each channel and I know it works with direct register access …
asked Sep 4 '16 by Luka
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Okay, it seems my understanding described in the question is correct. The AXI DMA does work as I described and the I2S controller also seems to work correctly. The problem was that I thought that … once TLAST is asserted it resets itself and the transfer continues, when in fact it immediately stops. I should've read how AXI stream works. So I needed to set the period register in the I2S
answered Sep 5 '16 by Luka