# Tag Info

17

As @duskwuff suspected, I've looked into this. To answer the question, the 8085 has two extra registers in the ALU. The 8085 has several "hidden" registers: a 16-bit WZ pair and two 8-bit ALU helper registers: ACT and TMP. WZ is part of the register file, while ACT, A (accumulator) and TMP are located in the ALU circuitry itself. Here's a diagram of how ...

7

The five flags on the 8080/8085 are Sign, Zero, Carry, Half-carry and Parity. It looks like your program clears all of them. The result of the ANI is not zero, not negative and has odd parity. Also, logical operations like ANI unconditionally clear both carry flags. Actually, the most direct way to set all of them is something like this: LXI H, 0FFFFh PUSH ...

7

Context Beforehand The earlier 8080A/8085 processor supported only a 16-bit address bus. At first, this wasn't much of a limitation as the cost of memory was quite high and many could not afford (nor at the time saw much need for) more than 65k. In the few cases where someone was willing to work for it, they would implement memory banking by providing an ...

6

The "extra" T state is designed into the cycle in order to give the external memory sufficient time to respond. Remember, when this chip was designed, the memory chips used the same basic technology as the processor, and were just as slow, plus additional time was required for external address decoding and bus buffering. The designers wanted to make it easy ...

5

When the 8085 starts up, it will start fetching instructions from address zero. It is thus necessary that the memory which is located there contain defined contents. That does not imply, however, that address zero must be mapped permanently to ROM. One could build a system with e.g. 2K of ROM, 64K of RAM, and a floppy drive, and use an I/O bit to control ...

5

You could use the old hacker/DYI debugger trick of mismatched stack push/pop operations, to directly set the flags register. ; terrible hack loads A and Flags ; regs D and E are used as temporary MVI D, #___ ; move immediate value for A MVI E, #___ ; move immediate value for Flags SZIH-P-C PUSH DE ; temporary POP PSW ; pop A and Flags Similar technique can ...

5

With something like an 8085 processor, the result is probably "undefined behavior". Those 1970s devices had limited logic available for instruction decoding, and they designed the opcodes to require minimal decoding effort. For example, maybe every op-code that had a '1' in the 4th bit would result in an update to the accumulator. These devices wouldn't ...

5

In synchronous designs it is an important task of designer to ensure such things do not happen. Register, which is having data being "clocked" into, is having specific dynamic properties like clock raise time, clock hold time, data stable prior and after clock signal change. If timing is violated, resulting state is not guaranteed. In your particular case ...

5

The accumulator is the ALU's output register. The 8085 has a two phase clock. Where single clock instruction like a NOP took 2 clock cycles. Similar to the 8088 used in the original IBM PC, the 8088 had a 4Mhz four phase clock and executed instruction at a rate of 1Mhz. With the two phase clock you have two oscillator cycles for each instruction cycle. ...

5

You must study binary arithmetic. Sign flag is not enough to identify the result of the signed addition. There should be another flag called overflow which will identify if resulting value is correct or not. 8085 does not have overflow bit, unlike Z80's P/V bit, and you will not be able to identify correctness of the result using S flag only. It will be ...

5

You DO have the equivalent of LDAX H in the 8085. But it's written as MOV A,M Because M is defined as "the address pointed to by the HL register pair". So, for the same reason, MOV M,A is the equivalent of STAX H

4

A microprocessor trainer is a big (and worthwhile) project, try to subdivide it into several smaller milestones. Trying to debug one massive project where nothing has ever yet worked, during the final week, is to be avoided... Consider the interfaces between the various parts and plan how to approach integration testing / debug. Since you have a fixed amount ...

4

The invalid opcodes would probably be interpreted as something and do something rather than acting as NOPs or causing "illegal instruction" traps, either of which would take additional hardware resources to decode and either nullify or trap. What that something is, for the 8085, I have no idea. However it shares many instructions with the contemporary (...

4

Minimum clock frequencies on parts of this vintage are typically an indicator that the CPU contains dynamic NMOS logic. Dynamic NMOS logic uses the gate capacitance of NMOS transistors to temporarily store data during an operation. Junction leakage in these transistors limits the lifetime of this temporarily stored data; as a result, this data may leak away ...

4

Regular 8085 "CALL" instruction must fetch the 16-bit subroutine address, so that makes it a 3-byte instruction (one for the 0xCD instruction fetch, two more for the following subroutine address). The "RST" instruction doesn't have to fetch an address, so that makes it a one-byte instruction (just the instruction fetch). A snippet of the address is ...

3

When I attended school we wire wrapped an 8088, which was great for several reasons. It was the last class to do so, later on I prepared a report for the professor and redid the entire project on a PCB (which was my first PCB and didn't work). I'll talk about these projects and what I learned from it, and what students need or should learn to prepare them ...

3

The $3$ machine cycles are: Opcode Fetch Cycle Memory Read Cycle Memory Write Cycle Internally, depending on the opcode, each machine cycle takes from $3$ to $6$ T-cycles (or T-states) to accomplish the $1$ machine cycle. T-states are one clock period long, and the instruction length is measured in T-states. For example, a typical Opcode Fetch ...

3

The 8085 requires ROM a the lowest memory address because, after a reset, it tries to fetch an instruction from location 0. If there was RAM at that address, the processor would fetch random data and would not start the program.

3

The 8085 has seven internal 8-bit registers for data, called A, B, C, D, E, H, and L. Six of these registers can also be used in pairs to hold 16-bit quantities. These pairs are BC, DE and HL, where B, D and H hold the MSB of the value and C, E and L hold the LSB, respectively. When these register pairs are transferred to/from memory, the LSB is always ...

3

Adding signed integers which yield a sum outside of the range of representation is formally invalid. To make it practically work, you would need software logic to figure out what happened and create a correct result in some viable representation, for example you could test that both operands were positive and re-interpret the result as a positive value in a ...

3

Latch can be used as a noun or as a verb. You got it right. ALE - Some IC's overlap Address bus and Data bus pins to minimize the number of pins needed. That means one pin can be used as an address pin or as a data pin depending on the current state of the bus. For the logic to work properly address value should be present for the whole read or write ...

3

In English, 'latch' is both a verb and a noun. In digital electronics, the usual distinction is that a latch is a memory gate with a level control: control input at one level for 'input flows through to output', control at opposite level for 'output held'. This differs from a flip-flop, which is typically edge-triggered. Your 8085 saves pins by ...

3

You are asking about the high 3 address lines, which are the 3 input bits to the 3 to 8 line decoder. All 8 possible combinations of A5-A7 (same as A13-A15 in this case) cause one of the 8 outputs to be asserted. It takes 011 to assert the output that drives the chip select of the 8255. The schematic is sloppily written in that the outputs of the decoder ...

3

The documentation for the 8085 says that after any arithmetic operation, for instance your SUB B, the parity flag is set if there are an even number of '1' bits in the accumulator. Perhaps you're not sure whether zero, the number of '1' bits in the 00H result, is odd or even. Zero is even. Odd numbers leave a remainder of 1 when divided by 2. Even numbers ...

3

it's late here and I may only help a little. But "ADD B" is a T4 type instruction, as you probably know. It also has been many years since I did anything with the 8085A and I apologize for any mistakes in advance. But here goes regarding the four T states of the "ADD B." (I'm just looking at the datasheet right now to refresh some of my ...

3

It would be insightful to analyse CALL instruction once more before talking about RET instruction. CALL INSTRUCTION IN 8085 As you stated, it consists of: Opcode Fetch, Memory Read, Memory Read, Memory Write, Memory Write 8085 follows decrement and push methodology while pushing to stack. Opcode Fetch in 8085 is typically 4 T states. However for CALL ...

3

In a write cycle, the CPU is driving the bus lines continuously, first with the address and then with the data. The bus is never tristated; the pattern of bits just changes at the indicated time. However, in a read cycle, the data is going to come from an external memory or I/O device, so the CPU must stop driving the bus at the end of the address phase so ...

3

There is an internal temporary register (not shown in the ISA documentation) that holds the second byte of the instruction while the third byte is being fetched. After that, the PC is updated with the full 16-bit value.

3

CALL is a 3-byte instruction. If the call is going to be taken, obviously all three bytes of the instruction need to be fetched so that the PC can be updated. Additional machine cycles are required to write the old PC to the stack. If the call is not going to be taken, the PC still needs to end up pointing to the next instruction after the CALL. The easiest ...

2

In the history of microprocessors the start was with very slow processors and very fast memory (a 6502 did a fetch, then execute, and in the execute phase the memory was free to be used for other purpsoes, like DMA or video generation). The Z80 had similar 'idle' period in the instruction execute that could be sued for DRAM refresh. With the generation of ...

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