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40

From looking at the last picture, we see that multiple votlages are mapped to the same discrete value, this means that some bits will not get transmitted/are lost. It seems we always have four repetitions that could be "pulled apart" again to form a nice continuous curve: This tells us that there must be two consecutive bits that are lost. After a ...


22

However because this is for a prototype that should be up to Industrial safety standards, my boss wants me to isolate the 10V from the 3.3V logic. I question your boss's logic when it comes to industrial standards: Where you need that level of isolation, I'd presume you want something very different than a raspberry pi running general purpose operating ...


18

I suspect that you have somehow reconstructed the order of the bits incorrectly. This may be simply a wiring error between the ADC and the FPGA, or you may have ordered the DDR data backwards, or the FPGA code has some kind of ordering error for the bits.


11

I would use an opto-coupler if this was a digital signal, but I am not sure if there is a way to achieve the same level of isolation while reading analog values. There is a product sold as a "precision linear optocoupler" for this purpose. Basically this is an optocoupler with one transmitting LED and two receivers. You use the second receiver to ...


9

I suggest using an ADC + MCU or maybe an MCU with an onboard ADC and transmitting the data digitally over the isolation barrier. Analog methods are possible (transformer methods are usually better than optoisolator), but it's difficult not to significantly compromise even a 10-bit ADC. If you want to avoid the MCU, you can find a single-chip solution to ...


6

Altering Vref would be a multiplicative scaling, that's not really going to be useful across the range of inputs in walking values across code thresholds a statistical fraction of the time as dithering attempts to do. For dithering you want additive noise, not multiplicative distortion that is functionally gain variation. Eg, you want to add various ...


6

Another option not mentioned above are "isolation amplifiers". They come in a couple of different flavours, but essentially act as analog buffers with isolation between the input and output. Really simple to implement, can have mediocre to excellent accuracy, can be expensive. Some examples: ADI AD210, TI ISO122, and SL Si892x


5

Use a voltage to frequency converter (VFC) to generate a square wave at a frequency proportional to the input voltage. Take this digital signal through an opto-isolator and then into a digital pin of the microcontroller - which then can be used to to decode the frequency into a voltage. There are still 8 pin VFC chips available - something like a LM331 - ...


4

Voice of (painful) experience: when using Microchip products, always check out the errata sheet. Your issue and a workaround are described in http://ww1.microchip.com/downloads/en/DeviceDoc/MCP3X5X-Family-Data-Sheet-Errata-DS80000845B.pdf .


4

Correct and the closer to 50 kHz (but above) the easier it is to make an effective anti-alias filter. But no need to go crazy about it. A 2nd order low-pass filter set at 100 kHz will provide 40 dB attenuation at 1 MHz and 80 dB attenuation at 10 MHz and, those aliased artefacts that might sneak through could easily become lower in amplitude than the ...


3

The best way IMO to accomplish that is to use an instrumentation op-amp with a ref input like the AD8220 which is designed for this purpose. They can take in differential voltage and output and offset-ed signal that can be directly connected to an ADC. The gain is simply set by an external resistor and the output can be offset by setting a voltage on the ref ...


2

Misundertanding in the working of for loop When your count = 4, unroll the loop to understand what happens in the hardware. You assign multiple vales to SDATA_ADC: SDATA_ADC <= ADDR_DATA (15); SDATA_ADC <= ADDR_DATA (14); . . SDATA_ADC <= ADDR_DATA (0); But only one serial data will be sent via SDATA_ADC in that clock edge, ie., ADDR_DATA (0). count ...


2

'Bandwidth' is one of those words that gets applied to many different things, so it doesn't have a concrete, context-free, definition. With a TDC, one context is the maximum and minimum frequencies that can be applied to the inputs, and still have the timing behave properly. Another one is the reciprocal of the smallest time difference that can be resolved ...


2

There are several possible causes for this CODE SPREAD. deterministic noise entering along with the signal; try 1,000 ohms in series, and 0.1uF capacitor from the ADC Analog VIn pin, to Ground (analog Ground?) with very short leads on the capacitor. is the MCU or ADC well bypassed, right at the AVDD pins? is the ADC VREF pin well bypassed, with the ...


2

The problem is that there are lots of codes output by the ADC that aren't valid BCD because they're the hex numbers A-F. The normal solution is "use a microcontroller", but I think there might be some binary-to-BCD or analogue-to-display converter chips in the 74LS catalogue?


2

If I am only interested in measuring the speed of the motor, do I only need to measure the frequency of the tacho signal? Yes, this will provide a more secure method for inferring speed but, at low speeds the voltage level p-p may be a tad low to adequately detect frequency unless you have provided a signal stage that uses (say) a comparator with a little ...


2

Fixed it, an oversight on my part. I was using the same state variables for both channels so thats why it sounded it was mixed together because it was using the old outputs of each channel to calculate a new value for the present channels.


2

No, while it could work on DC, the capacitors would shunt the PWM output directly. However Atmel/Microchip has an application note AVR121 which explains use of dither.


2

From your original equation we can elimate the division like this: $$ \begin{align} Setpoint_{RPM}&=ADC_{POT}\cdot\frac{Range_{RPM}}{2^N-1}\tag{1}\\\\ Setpoint_{RPM}&=ADC_{POT}\cdot K\tag{2} \end{align} $$ where K is a constant that can be pre-calculated to get rid of the division: $$ \frac{100}{255}=0.3921568627450980392156862745098\tag{3} $$...


1

ADIF is the interrupt flag. Unless the associated interrupt is enabled, you need to specifically clear that flag as you’ve mentioned. ADSC is the conversion complete flag. Which is set first? Probably both as one would think there would be only one mechanism internally to flag completion. I’ve always used ADSC. ADIF is used by those that don’t read the ...


1

The following should work. simulate this circuit – Schematic created using CircuitLab R1 and R2 divide down the input voltage by a factor of about 1/4 (0.2492) to make voltage X. X = 2.492V when +12V_BAT is 10V. X = 2.991V when +12V_BAT is 12V. The difference between X and 3V_REF is amplified by a factor of about 5.9. The overall equation for the ...


1

It may help you to think of voltage and current transformers as being complimentary. Voltage transformers are unloaded when open-circuit. They don't like short-circuits. Current transformers are unloaded when short-circuited. They don't like open-circuits. If you open-circuit a CT secondary and drive a current through the primary then the CT output voltage ...


1

It is a must to keep the burden of a current transformer always connected across its secondary winding. This is to eliminate the danger of high voltage induced in the secondary winding that could also result in damage to the current transformer caused by insulation breakdown. This applies equally to the dual windings of a current transformer intended for ...


1

For the Finite State Machine (FSM), you need to clearly define your inputs, outputs, states, and transitions. And for VHDL-2008, sensitivity lists are a thing of the past (they used to cause lots of bugs due to simulator/synthesiser mismatches). They have been replaced with process(all). States This is an example of state names you could use without using a ...


1

Sounds ok to me. I've implemented PID too for a power device using PWM. Ensure you're resetting the PWM at zero crossing. Also you might want to consider how frequently you can update the PWM value. I mean , the comparison in FPGA would be much faster than the loop. Consider soft-starting if you need.


1

Your plan seems sensible in general. I have constructed similar things and it works like you are describing.


1

Why waste FPGA logic on such calculation? Use an SPI / I2C based potentiometer. Only two potential limitations would be that the speed of change of resistance and the rate at which the SPI / I2C can update the potentiometer value the second limitation being low wattage for this option. I'm sure it would reduce BOM cost and also PCB space, along with better ...


1

the STM32 has an Analog watchdog, which sets a flag when an ADC channel is above or below 2 predefined tresholds. in the worst case of polling zero cross, you can just read this status bit, clear it, wait a little (based on your sampling time) and read it again to see if it got set. the good thing is, the tresholds make a good margin for neglecting noise. (e....


1

Reading 4 wire RTDs with good/very good accuracy is not a trivial task. As previously mentioned, accurate current sources are needed to biasing the PT1000 resistances. VRef kind of sourcing can seem at first instance enough, but surely will not very accurate task. Not only possible VRef fluctuations, but also ADC side effects (input kick-backs etc.). Thus an ...


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