# Tag Info

20

The green boxes are IO pins, the blue lines are wires, the red boxes are configuration bits, and the grey boxes are logic blocks. The red boxes can supply a constant logic 0 or logic 1 to whatever they're connected to. Each logic block implements a 3 input, 1 output look-up table (the combination of the logic levels of the three inputs determines which ...

19

Do you know how to check for divisibility by 9 in base 10? Add all the digits using base 10 arithmetic. If the result has multiple digits, repeat the process. Stop when you have one digit. If the digit is 9, the original number was divisible by 9. This works because the divisor being tested is base-1. For instance 45 is divisible by 9, and the digits sum to ...

9

If I were doing a silicon implementation, I would use an XOR because of the symmetric properties. Symmetric circuits use much less power because the stack size is the same that does a few useful things: Greater effective serial resistance when "off" due to the "stack of 2", Better matched channels because DIBL is the same on pull up and pull down networks,...

8

Of course there is. First we write out the truth table: Y S 000 000000 001 000001 010 000100 011 001001 100 010000 101 011001 110 100100 111 110001 We notice right away that S0 = Y0, S1 = 0, and S5 = Y1 * Y2. Let's remove those. Y S 210 432 000 000 001 000 010 001 011 010 100 100 101 110 110 001 111 100 And now we see that S2 = Y1 * !Y0, S3 = Y0 *...

8

What you are really asking is whether you can drive a LED directly from a digital signal, or whether it should be buffered by a transistor. Think about it. This has nothing to do with a adder or whether it is 4 bits wide or not. The answer depends on the current capability of the digital output, and how much current you want to drive thru your LED. This ...

8

You posted your own explanation. Take a closer look at your own image: The red box is meant as a label box for you to write into with a value or signal, and represents the signal that controls the switch that connects a horizontal wire with a vertical wire (the green lines). The horizontal wires and vertical wires are not connected at the junction when they ...

7

A system of ripple-carry adders is a sequence of standard full adders that makes it possible to add numbers that contain more bits than that of a single full adder. Each full adder has a carryin (Cin) and a carryout (Cout) bit, and the adders are connected by connecting Cout on step k to Cin on step k+1 (Cin on step 0 is C0 in the picture, Cout on step 3 is ...

7

There is a distinction between parallel adder vs serial adder. Both are binary adders, of course, since are used on bit-represented numbers. Parallel adder is a combinatorial circuit (not clocked, does not have any memory and feedback) adding every bit position of the operands in the same time. Thus it is requiring number of bit-adders(full adders + 1 half ...

7

It's probably most straight forward using a NOR form as the basis of a BJT adder. It's quite simple to form the basic gate, this way. Nothing crazy, at all. Just simplicity. The following schematic shows the basic one-BJT form for the NOR gate at the top. It then follows up by showing what a full adder would look like if it were based entirely on these ...

6

(Cheat) The simplest yet most powerful solution is to use a Flash memory as a lookup table for the results. 8-bit A input + 8-bit B input + 3 bits operation code is 19 bits. Pick a 512 k $\times$ 16 bit Flash (about \$2), use the 19 input lines as address, and program it with the results for each input combination. This way you can have any operation you ...

6

Use an op-amp mixer circuit. This will add three signals into one: - Alternatively, if you did the math you would find that three independent voltage sources connected together thru 3 resistors of equal value would produce a node voltage that is the average of the three voltages. This might be easier: -

6

You're making a couple of assumptions: Multiple outputs can be connected directly together When any such output is "high", then the wire is "high". This is known as "wired-OR", and indeed, such circuits can be constructed. They rely on special features of the circuits of the previous outputs to create the logic function you're looking for. However, a ...

6

Premature optimization is the root of all evil. --Donald Knuth If you want to do it efficiently, let the synthesis tools choose the best implementation. Just use an HDL to describe the behavior you want. Most FPGAs include some kind of optimized structures for addition, and if you try to force the synthesizer to use some bizarre method that looks good on ...

6

Both have their uses: The second gives potentially better hardware in a real-life scenario, the first can be given to students as coursework for a course named "history of hardware" or something equivalent. For the second example, the synthesis tool will implement an addition in whichever way works best for the set boundary conditions. This might be a full ...

5

The simplest approach would be to decode the x y z inputs into eight lines. Then from these, you implement logic which drives chip select lines to enable the appropriate unit which handles the inputs, as well as any transformations that are needed so that the unit performs the correct operation. I don't think you can use an adder for your logic operations ...

5

How does Logisim handle xor gates without exactly two inputs? A two-input xor gate should have an output which is true if one input is true and the other is false, but it's not completely unambiguous from just that description how that should be generalized to N inputs. The normal approach is to say that the output of an XOR gate of any size should be true ...

5

Some aspects of a system can be made to use arbitrary data widths, though there are often relationships between different parts of a system. For example, in most cases the number of words per instruction or instructions per word would vary with the data width. One likely wouldn't want to try to use four-bit instructions even if one used a four-bit data ...

5

Not really. You can for some purposes set up an array of 4-bit computation units to act on a 256 bit word, but many operations have interdependence between the bits, for example the carry in addition and subtraction. Within a stage, special look-ahead carry generation is used to make sure that the more significant bits get their carry input in time to ...

5

The blocks labeled "FA" are called full adders, and they are fundamental to how binary arithmetic is done at the gate level. The circuit you have presented here is an implementation of a 4-bit adder/subtractor. Combining addition and subtraction in the same operation requires the use of an alternative representation of binary numbers. This is called 2's ...

5

0 + 0 = 0 0 0 + 1 = 0 1 1 + 0 = 0 1 1 + 1 = 1 0 The ones place of a single-bit addition is equivalent to the exclusive OR operation, not the OR operation. Hence XOR is used instead. Note that this is not the only way to build a half adder, you can do it without using an XOR gate, but it requires more gates. For example, here is a half adder built with ...

5

It's important to understand there's a difference between a half-adder and a full-adder. A half-adder is the simplest. It has 2 inputs and 2 outputs. It's basically a XOR. The primary output is only 1 if one of both inputs is 1, but not if both are 1. That's Sum. The second output is only 1 if both inputs are 1. That's Carry. That's nice, but only if you'...

5

Besides what is said by those who replied earlier, Carry can also mean an input coming from the flag register that allows linking one sum on a ALU to the next one. By linking I mean that, if your computer architecture has a ALU with a word size of 8 bits and you need to do a 16 bit sum, the ALU can use the Carry flag, placing it on its carry in as a way to ...

5

The green lines are wires, the red boxes are connections, you can connect a green wire to a block with a switch. The switch is in the red block and it can connect two wires together if enabled. This is how many modern FPGA's work. But instead of having to do this by hand, a hardware synthesizer figures it out for you. Heck, by the time you finish this ...

4

If you want to add two voltages together without introducing an inversion it's very easy. Here's one where three voltages are added but remember the output is an average of the three (or two or however many sources you wish to add): - Next, you need to provide a gain stage from an op-amp so that the "3" part in the denominator is converted to "1". In the ...

4

The purpose of the "carry" in is to accept the "carry" out of the previous adder. Carry works just like normal arithmetic.

4

It really isn't worth worrying too much about this detail. Adding 1 to a number is such a common idiom in HDL that synthesis tools have highly-evolved methods for dealing wtih it. Also, most modern FPGAs have dedicated, hard-wired fast carry logic that does not consume logic cells, and that synthesis tools know how to take advantage of.

4

Ripple carry and carry lookahead adders are combinatorial circuits - they do not hold state and they are not clocked. So counting clock cycles is meaningless, unless perhaps you are talking about some sort of a pipelined implementation. Generally the whole point of using something like a carry lookahead adder is that the addition operation will be ...

4

The technique is similar to what you would do to check if a number is divisible by 9 in decimal. We need split the number into four bit digits and then add the digits together repeatedly until we have a single digit left. Lets call the digits X Y Z c1,r1 = X + Y c2,r2 = Z + r1 + c1 c3,r3 = r2 + 1 IF X,Y,Z is divisible by 15 then c2,r2 is also divisible by ...

4

The idea here is that you can treat a BCD digit as a single entity. Look at the components you have: 1-digit adder Multiplexer (presumably for BCD digits) 9's complement unit All of these use full BCD digits for their inputs and outputs, so you don't have to think about the individual bits. $C$ and $ADD$ are binary, but they never combine with the BCD ...

3

This problem only has 8 possible inputs, so a lookup table could be a good answer, especially if this will be inside a FPGA.

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