# Tag Info

Accepted

### I am unable to figure out how the answer to following question is 70ns

You have to check the longest path through the design. In this case it involves the carry, because that goes through all the adders. The question isn't clear whether the output that is considered in ...
• 57.7k
Accepted

### Is it usual design that the addition operation in the arithmetic-logic unit is performed by default as other instructions are executed?

From the above discussion, I'd like to expose you to a variety of ideas so that you can more readily see the scope of the reality of CPU designs and perhaps gather up the difficulty in trying to say ...
• 69k
Accepted

### Is there a way of converting easily binary numbers to its ASCII equivalent?

I actually did all the ASCII to binary and the addition part easily with multipliers and adders That's quite complicated. You don't need multipliers. You have a number in the BCD form, and you can ...
Accepted

### Does a 64-bit computer require 64 full adders to perform additions/subtractions, or would it somehow require less?

if you wanted to do 64-bit addition, would you need to have 64 full adders together? Yes. I'm also curious how many adder circuits a typical modern desktop would have Broadly this is the number of &...
• 45k

### Minimizing delay of Full Adder

The boolean equation for $C_o$ in Full Adder is: $$C_o = A.B + C_i(A+B)$$ Implementing above expression in CMOS logic will give you its complementary version at the output of Full Adder cell: \...
• 10.3k

### Is there a way of converting easily binary numbers to its ASCII equivalent?

What you're looking for is called a "binary to BCD" circuit. There are ICs for this. You need to convert the 8 bit binary natural number to three 4 bit binary coded decimal digits (and of ...
• 714
1 vote

### Is it mandatory to sign-extend when adding two different-sized buses?

Supposing your numbers are in 2 complement form. Lets call XY the 32 bits number (X being the 16 most significan bits, Y the 16 least significant bits). Lets call Z the 16 bits number and S its sign ...
• 2,573
1 vote

### 1-bit Full Adder is a universal gate, like NAND gate?

According to the site Electrical4U A universal gate is a logic gate which can implement any Boolean function without the need to use any other type of logic gate. [my emphasis] The NOR gate and NAND ...
• 1,399
1 vote

### Carry bypass adder delay higher than expected with timing analysis

The answer to your question will be found in the utilization and timing reports from the FPGA tool (Quartus you said). What you are missing might be the fact that FPGAs have hard adder resources. So ...
1 vote

### Tensor core makeup

GPUs are arithmetic-optimized arrays of compute cores. They have fairly extensive math-oriented instruction sets that handle a wide palette graphics workloads. They are an evolution of ‘vector ...
• 40.3k
1 vote

### Full adder Cout expression issue

If you drew up a truth table for the expression you found, you'd realise that it would exactly the same as the one for the expression they've given you (so you're not wrong). Since you would already ...
• 190
1 vote
Accepted

### Bits are toggled in step 1 or 9's complement is done using subtraction?

Using an adder makes it easier than using a subtractor, less logic, easier to understand, etc. In grade school we learned a - b = a + (-b). And our first computer class we learned about this thing ...
• 7,948
1 vote

### Integrating an AND gate into another logic gate

The circuit you showed us here is not a logic gate. It's something that creates light (or not) depending on the positions of switches. In other words, your circuit converts certain combinations of ...
• 7,090

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