# Tag Info

38

This possibly answers the title of the question, if not the body: Floating point addition requires aligning the two mantissa's before adding them (depending on the difference between the two exponents), potentially requiring a large variable amount of shift before the adder. Then renormalizing the result of the mantissa addition might be needed, ...

30

Typically high resolution sin(x) functions would be implemented with a CORDIC (COrdiate Rotation DIgital Computer) algorithm, which can be accomplished with a small number of iterations using only shifts and add/subtract and a small lookup table. The original paper The CORDIC Computing Technique by Jack Volder is from 1959. It also works nicely when ...

24

Ah, you're missing the STATE MACHINE concept. That's where we can "write code" made out of TTL hardware chips: data-selectors, 4-bit counters, gangs of parallel flipflops. (But all those are the complicated parts, while the idea behind "state machines" is fairly simple.) "State-machine" is also commonly called "micro-code." Also called "bit-slice" or "...

23

In FP multiplication, exponent processing turns out to be simple addition (for exactly the same reason that multiplication in the log domain is merely addition). You have come across logarithms, I hope. Now consider how difficult it is to add two numbers in logarithmic form... Floating point inhabits a grey area between the linear and log domains, with ...

18

TL:DR: because Intel thought SSE/AVX FP add latency was more important than throughput, they chose not to run it on the FMA units in Haswell/Broadwell. Haswell runs (SIMD) FP multiply on the same execution units as FMA (Fused Multiply-Add), of which it has two because some FP-intensive code can use mostly FMAs to do 2 FLOPs per instruction. Same 5 cycle ...

17

As @duskwuff suspected, I've looked into this. To answer the question, the 8085 has two extra registers in the ALU. The 8085 has several "hidden" registers: a 16-bit WZ pair and two 8-bit ALU helper registers: ACT and TMP. WZ is part of the register file, while ACT, A (accumulator) and TMP are located in the ALU circuitry itself. Here's a diagram of how ...

14

Most computer trig libraries are based on polynomial approximations, which gives the best balance between speed an accuracy. For example, a dozen or so multiplication and add/subtract operations is enough to give full single-precision accuracy for sine and cosine.

13

Yes, when written as multiplication in normal math, it means AND in Boolean logic. This does make some sense when you think about it. Make a truth table of multiplying two value that can be either 0 or 1. The result is 0 except when both are 1, then the result is 1. That's exactly what AND does. This logic doesn't really follow for "+", unless you ...

11

No, it's not a multiplexer. A multiplexer would select one of both inputs, in an ALU both inputs may be used simultaneously, depending on the pending operation. ALU stands for Arithmetic and Logic Unit, and those are the types of operations it performs. If the operation calls for a left shift of register R1, then the second input is ignored, but you ...

10

The CU (Control Unit) is responsible for all data transport to and from the ALU. The ALU doesn't see buses, it sees two N-bit wide inputs, and ditto output. The CU must make sure that both inputs of the ALU are loaded (latches) with the required data. When the ALU has performed the operation the CU will route the output via internal (and possibly external) ...

9

A single 32-bit x 32-bit to 32-bit lookup table would require an untenable amount of space: $$2^{32} \times 2^{32} \times 32 = 2^{69} \approx \mathrm{5.9\ quintillion\ bits}$$ This is flatly impossible to build. A single microchip can store perhaps 240 bits (~128 GB); you'd need over 500 million of these to store the full lookup table. (Halving the size ...

8

That's essentially it. The technique is called bit-slicing: Bit slicing is a technique for constructing a processor from modules of smaller bit width. Each of these components processes one bit field or "slice" of an operand. The grouped processing components would then have the capability to process the chosen full word-length of a particular ...

8

As others have noted, an ALU's function is to perform (typically either binary or unary) arithmetic and logical operations on input busses. You can break an ALU down into three primary stages along with some control logic that configures those stages. Argument Selection: this stage really really is just a Multiplexer for each input that allows for the ...

8

You can manipulate arbitrarily wide numbers using a finite width ALU. However, multiple operations are required when the number is wider than the ALU. To illustrate this, I'll use a PIC 18 as example. This architecture can manipulate only 8 bit numbers directly. To add the 8 bit quantities VAR1 and VAR2 and put the result into SUM would take code like ...

8

In an unsigned binary representation, only positive numbers can be represented, and the weight of each bit including the most significant bit is a power of two. So with a word size of 8 (byte), 00000000 => 0 01111111 => 127 10000000 => 128 11111111 => 255 Two's-complement, which is used for signed binary notation, encodes both positive and ...

8

I'm going to look at this part: "Why is it that they would allow"... TL;DR - because they designed it that way. It is a management decision. Sure there are answers of mantissa and bit shifters, but these are things that go into the management decision. Why did they design it that way? The answer is that the specs are made to meet certain goals. Those ...

7

Delayed branch and branch prediction are two different ways of mitigating the effects of a long execution pipeline. Without them, the pipeline needs to stall whenever a conditional branch is taken, because the instruction fetch mechanism can't know which instruction should be executed next after the branch instruction until the computations on which it ...

7

As with many texts written for beginners the situation has been somewhat simplified. The assumption is that a 32-bit processor does all address operations and calculations also in 32 bits. From that it assumes a 32-bit address bus. Therefore the maximum address range is 4GBytes. That same reasoning is then extended to a 64-bit processor. In real life it ...

7

A processor is really a finite state machine (FSM) for implementing the machine code instructions. It reads the instructions from memory and uses the required hardware, such as the ALU, to implement them. Here is the data path of the MIPS architecture. source You have a control unit implementing said FSM and is responsible for ensuring the data is ...

6

At the very lowest level, consider something like microcode. That's what Wouter was talking about when he mentioned Very Long Instruction Word architectures. A CPU is a collection of busses, registers, memory, and arithmetic logic unit (ALU). Each of these do simple and finite things. Any one higher level instruction is a coordinated set of actions ...

6

To me the ALU seems like a multiplexer ... An ALU performs many tasks. A multiplexer essentially performs one task. An ALU could be given a multiplexer function as one of it's features if desired. ie a multiplexer's capabilities may be a small subset of an ALU's capabilities. In a typical implementation, both have two inputs and one output. But the ...

6

(Cheat) The simplest yet most powerful solution is to use a Flash memory as a lookup table for the results. 8-bit A input + 8-bit B input + 3 bits operation code is 19 bits. Pick a 512 k $\times$ 16 bit Flash (about \$2), use the 19 input lines as address, and program it with the results for each input combination. This way you can have any operation you ...

6

A SRAM memory which is many kilobytes or megabytes in size will generally be constructed in such a way as to minimize the surface area per bit. A typical design will have memory cells aranged on a grid. Each memory cell will have four transistors to hold each bit, and two "access enable" transistors to connect each bit to normal and inverted buses which ...

6

The basic idea is that the adder after the abext cells can do the heavy lifting needed for the first few operations, with some simple transformations of the inputs. Some options (not sure if these are all optimal): A + B → ia = A, ib = B, cin = 0 A - B → hint: do you know how to convert B to 2's complement? A + 1 → ia = A, ib = 0, cin = 1 A → ia = A, ib = ...

6

In 2's complement the MSb is defined as -(2n) where n is the bit position of the MSb. Due to how numbers work, all bits other than the MSb add up to (2n)-1. Adding those together results in -1.

6

You're making a couple of assumptions: Multiple outputs can be connected directly together When any such output is "high", then the wire is "high". This is known as "wired-OR", and indeed, such circuits can be constructed. They rely on special features of the circuits of the previous outputs to create the logic function you're looking for. However, a ...

6

This diagram from Intel may help: It appears they've given each unit a FMA (fused multiply-add) as well as a multiply and a single adder. They may or may not share hardware underneath. The question of why is a lot harder to answer without internal design rationales, but the text in the purple box gives us a hint with "doubles peak FLOPs": the processor ...

5

The simplest approach would be to decode the x y z inputs into eight lines. Then from these, you implement logic which drives chip select lines to enable the appropriate unit which handles the inputs, as well as any transformations that are needed so that the unit performs the correct operation. I don't think you can use an adder for your logic operations ...

5

It depends, but usually no, because carry 64 bits of carry propagation would be way too slow in most cases. It is more common to use either a lookup table to implement a wider adder than 1-bit or direct implementation of a larger adder in boolean logic, and chain them together with carry-propagation. This is particularly true not so much for the ALU, which ...

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