The logical effort of the entire gate is the ratio of its output logical effort to the sum of its input logical efforts. The answer depends on a schematics of your mux. It may happen that you need to consider all the signal paths within multiplexer.
Option 1 is how I've seen it and how I've designed it for integer inversion.
The "add 1" takes one cycle and the bit inversion is absorbed in the same cycle.
For subtraction, the same adder with inverter is used, and the "add 1" is applied through the carry-in for the LSB, and so it costs no extra cycles.
I found this post for the same reason as the OP - trying to implement zr for the ALU in The Elements of Computing course.
zr is 1 if the ALU output is 0, 0 otherwise
The course provides a hardware simulator and a range of built-in predefined chips.
One of the built-in chips is an 8-way OR gate. An 8-way NOR gate is not provided. The ALU is 16-bit. I split ...