# Tag Info

10

I have a hard time understanding how the oscillator works in this circuit. The oscillator uses varicap diodes V1 to change the frequency of oscillation. It's a bog-standard common-collector Colpitts oscillator: - But this circuit is very different from a standard Colpitts oscillator which uses two capacitors and an inductor. No, it's a standard ...

8

This is a little like: An amateur astronomer asking if they need to understand optics, when all they need to do is buy a telescope and apply it. A response here is that so long as their intent is to use the telescope as a toy and to not use it to help professional astronomers, then that's fine. But, otherwise, they need to understand the various kinds of ...

8

I think this is a common misunderstanding of the "transition frequency" characteristic of transistors / opamps. A transition frequency of 300 MHz doesn't mean the transistor "works" up to 300 MHz. It means above 300 MHz it will be completely useless (gain < 1, no matter what operation mode you use). Practical schematics expect ...

5

Why does this transistor oscillator not work at 100 MHz? In one of your previous questions, I proposed this 100 MHz oscillator circuit: - As you can see, L1 is about ten times what you are using and C1 and C2 are also much smaller than what you propose in your circuit. You also need to use a transistor that has got a decent β into the GHz, possibly a BFR90 ...

5

But this circuit is very different from a standard Colpitts oscillator which uses two capacitors and an inductor. In a standard Colpitts oscillator the gap between capacitors is grounded, while it's connected to resistor R8 here. Why? This is an awful lot like a standard Colpitts oscillator, you're just not thinking flexibly enough. To understand all the ...

4

I think what you are getting at is that you may not need to know transistor-level design since you can just use integrated circuits (such as an op-amp). Op-amps are analog components, so designing a circuit with an op-amp would be considered analog design. You can use an op-amp without knowing how it works at the transistor level. But sometimes knowing how ...

4

You can usually cause the simulation to work okay if you use the initial conditions card, .IC, in your schematic project to set an unusual node voltage as a starting point. (You could also add a starting pulse using a PWL current source and a diode, for example. But that's more complicated to do.) That said, your specific schematic does run under LTspice ...

4

You need to add an active pull-up stage to the output, rather then just relying on the collector resistor to pull the collector voltage up. Look at what's used in a typical TTL output stage, what's called a totem-pole output structure. Look at this question: TTL, Totem Pole vs. Open Collector Output

3

A small-signal analysis deals with the change in the response of a linear circuit as a consequence of a small-signal excitation superimposed in addition to the circuit's DC condition. A small-signal model of an ideal current source is simply an open circuit (i.e. infinite impedance) - no additional current flows through that branch regardless of what you do. ...

3

The comparator isn't 'active' when the inputs are more than a few mV different in voltage, it's saturated to one rail or the other. The important parameters, propagation delay and input offset, are a function of how the comparator amplifier behaves when in the linear region.

3

You've chosen a transistor that doesn't have much gain at $100\mathrm{MHz}$, and Your tank circuit's characteristic impedance is much, much too low. I don't have data for a 2N2222 handy, but the data sheet I have on hand for a 2N3904 lists an $f_T$ of $250\mathrm{MHz}$. You can make a transistor oscillate at or below its $f_T$, but things get ...

3

No. That violates the Vin > Vdd spec. and causes latchup failure. But you could add series > 10k and Schottky diode or 3V Zener or 470 R and white LED at 3.1V. But depends on speed and load capacitance.

2

In all but a few special cases, the inputs to an IC cannot go outside of the power rails by more than a few tens of mV, and it's typical to see chips specified to have inputs limited to exactly the power rails or less. This is because most chips have ESD protection on their inputs that's implemented with diodes to VSS and VDD, or their inputs just have ...

2

My recollection of a "free standing" oscillator is that it has positive feedback in the circuit and it depends on the amplification of component noise to start oscillating. The real world noise and startup conditions are not easily duplicated in a simulator model so one might need to apply tips and tricks to simulate the oscillator. This reference ...

2

Yes, Especially ceramic capacitor will be affected. Their capacitance can vary greatly over the specified voltage. More information in this Kemet note: https://www.digikey.com/Site/Global/Layouts/DownloadPdf.ashx In practice, you can often overcome the problem with polymer film capacitors.

1

There is probably a simpler approach, but here’s how you can do it by mapping it into the Z-Transform. Perform the Z-Transform mapping of your choice (bilinear transform is pretty popular). Use the Z-Transform to find the residues of the system. Use the residues to find the difference equation of the equivalent digital system. Make sure to pay attention ...

1

May I know when Enable is high, can I assume both I/P (S0-S2) and O/P(Z) are at high impedance state. Focus on the last line of the table in your question: - A switch being off will mean high impedance. Inputs S0 to S2 will remain high impedance (because they are inputs) irrespective of the state of the enable input.

1

The analog output step change should follow the max scan rate which is 100 kHz. Meaning that the analog output for each successive step should change/settle fast and accuarte enough in 1/100 kHz = 0.01 ms. This is not the correct way to think about your problem. What you are really doing is providing an analog signal, which is continuously varying from -2....

1

The answer from SteveSh is one reason for a slow rise time. Another is that saturation in Q3 will cause it to be slow to turn-off. One improvement that can be done is to add a small capacitor across R7, maybe 100pF. This will cause a negative base current and more quickly turn-off Q3. Also a resistor from Q4 collector to ground, maybe 1k, will help speed up ...

1

The oscillation happens at the frequency where the total phase shift of the amplifier and feedback circuit is exactly 360 degrees or its multiple- including zero degrees. The amp does not in this case invert the phase, but heavy capacitive load causes phase lag - tens of degrees. But the phase shift of the LC circuit cancels it and that happens near the ...

1

The spikes in Id show a clear lack of deadband in the crossover timing. Correct that with suitable 1us +/-50% delays with asymmetric rise times to gate or inputs using a diode // R. (I.e fast turn off, slow turn on) consult App notes for details.

1

You can show the result for both filters using a simulator: - The blue trace is just the 320 kΩ resistor and 680 pF capacitor. The red trace is the same filter but with the 5 kΩ and 39 pF filter buffered on the back of it: - So, Vout1 has a 3.01 dB point at 731.360 Hz and Vout2 has a 3.01 dB point at 496.177 Hz. Vout1 is a single order low-pass filter and ...

1

When any amplifier saturates the gain is zero. When analyzing the small-signal performance of a comparator, we assume it is not saturated and thus operates in the linear region, which is rather difficult as it is not unity gain compensated to do so but may perform well in an open loop with low offset. This means comparators are not designed for linear ...

1

The circuit simulates well, but at higher frequencies begins to climb again to almost the original value. I used an ideal op amp for the simulation. I believe that the problem is here is that your op-amp supply is not adequately referenced to ground or 0 volts (the triangle symbol). Maybe use two series 2.5 volt supplies with the centre connection tied to ...

1

Think of Ro as a resistor in parallel with the FET's source-drain (it's not quite that). In the circuit above, the DC value of VIN would be chosen to allow the FET to be biased correctly -- the drain would sink a current of exactly I1 and the drain V would be at about VDD/2. Now, for small perturbations in VIN, the drain current -- ID of the intrinsic FET ...

1

This will work just fine although you should keep in mind that R57 will be in series with R47. You can leave out R57 and just connect the Z pin directly to Vcc. An even simpler solution would be the 74HC238, which is a digital demultiplexer (instead of an analog one). You could even eliminate the transistor with a 74HC238; the chip is powerful enough to ...

1

With the 555 timer I believe there is a normally a discrepancy at higher frequencies between the calculated frequency (using the data sheet equations) and the actual output frequency. This discrepancy increases as the set frequency increases with the calculated frequency always being higher in value than the actual measured output frequency. I believe this ...

1

A simulator has identical components, so both transistors conduct equal amount and there is no imbalance to start the oscillation. In real world, non-idealities of components means that always one of the transistors will conduct first and the oscillation starts. Therefore, to simulate oscillators, the non-idealities must be edited in to the components by ...

1

When you pass the button trigger through a capacitor, and pull it up on both sides like this, you can quite easily generate a short pulse. This way, when the button (red) is low for a longer time, the trigger level (green) will pull up instantly. This results in a short pulse and a desired output (blue). Of course, values should be changed when the timings ...

1

It doesn't have to be ground. In the Low Pass Filter, the capacitor needs to be connected to an AC ground. This basically means a constant (DC) offset from true (signal) ground. So, it could be connected to a 5 V battery (the other end of which is connected to ground). This could have some subtle implications when the circuit starts up, but from a signal ...

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