# Tag Info

## Hot answers tagged analog

22

The big advantage of the 50% power point is its symmetry : if you interchange the R and C in the classic low pass filter in Andy's answer, you get a high pass filter with the same cutoff frequency. If you chose any other point (such as 50% of voltage, 25% of power) you would still get a high pass filter ... but you would have to re-calculate the cutoff ...

19

Why 70.7%? Why not 50% or 20%? When a voltage drops to 70.7%, the effective power it can produce into a resistive load is halved. So, the important thing to note is that a 50% power reduction is equivalent to the voltage reducing to $\sqrt{0.50} = 0.70710678$ or 70.7% approximately. Why 50% power and 70.71% voltage in a simple RC filter? If you take a ...

7

What is the advantage of RLC low pass filter over two RC connected in series? With two RC low pass filters in series, the Q can never be greater than 0.5 and therefore it cannot make use of the peaking effects you get when you use an RLC low pass filter such as this one: - Picture from here. Look at the red trace - around resonance you can achieve a ...

6

Well - it is not a simple task to explain WHY a certain definition was agreed upon. Of course, such a definition for the end of a passband should "make sense". But what does this mean? One possible explanation is - as mentioned in the existing contributions - based on power considerations. As another explanation the PHASE SHIFT could be used. Because such a ...

6

It must be a per cent mille (milli per cent) or 10⁻⁵. I have no idea why TI decided to use such an obscure unit in a data sheet. It is occasionally used in other fields of engineering, but I have never seen it used in electronics.

4

Assuming you're talking about figure 33, looks like they're plotting 1000x the error in %. So milli-percent. Maximum gain error is 0.047% so that would be 47, which fits with the graph.

4

The answer is, yes for analog VGA, blanking is required (that is, porches set to analog black), as set out in the VESA specification for each display format. Why? The RGB signal can be (and often is) offset from 0V, especially if sync-on-green is in use. So the receiver needs to sample analog black just after sync and use it as reference for the remainder ...

4

If your microcontroller does not have a DAC, you can generate high-frequency pwm, run it through a low pass filter and it is effectively an analog voltage. Unfortunately if you're trying to get up to a higher rail voltage than your microcontroller pin output, then you could either first pwm a transistor in front of the filter with a pull down from a higher ...

4

I think it's a case of mistaken identity: -

3

The cutoff is at 50% power, which is - 3dB. This is by convention. For voltage, we calculate the Vo/Vi ratio in dB as 20 log(10) Vo/Vi. Plugging - 3 into this equation for Vo/Vi yields 0.707 which is also sin45 and cos45.

3

Because 70.7% of output voltage means the half of the initial power: $$P = \frac{V^2}{R_L}\\ P'=\frac{(0.707\ V)^2}{R} = 0.5\ \frac{V^2}{R_L} = 0.5\ P$$ If you ask "Why the half of the initial power", it has no explanation (at least, I don't know). Maybe about audio, or maybe another thing. All we know is, the point where the initial power is reduced to ...

3

Is there any disadvantage with transmitting the same excitation signal to several resolvers (basically rotating transformers)? Well, going back to some old-fashioned positional systems used on-board ships (for instance), that's exactly what they did and there was no option. One synchronous resolver was operated manually from some desk /back-office ...

2

I can forsee several possible issues with what you're proposing. One, the reference excitation drive is probably gain-controlled based on the return signals, so its drive is tuned and adjusted specific to that resolver. The decoder relies on knowing that reference to properly demodulate the X and Y return signals. Two, impedance control and signal ...

2

This does what you are asking with one dual op-amp. R1 and R3 give the gain of 16, and R2 increases the gain when the input voltage rises above 250mV. OA2 saturates to the positive supply for lower inputs. Since temperature is the variable, presumably speed is not of concern. simulate this circuit – Schematic created using CircuitLab

2

Use a DAC followed by a non-inverting op-amp based amplifier.

2

First of all, you can't convert 8 bits binary to EXACTLY one BCD, you'll need 3 BCD converters: the maximum value with 8 bits is 255, supposing you have unsigned numbers, so 3 digits are needed. You have two choices: Use asynchronous solution There's an algorithm "Double dabble" that does the conversion from binary to BCD. You can start from here: Double ...

2

They mean "functionality". Basically, a digital function is one where the voltage levels are well defined to mean a number -- almost always a 1 or 0, but search on "four level memory" and "trinary logic" for exceptions. Digital logic defines some voltage range (usually close to zero volts) as '0', some other voltage range (usually close to the supply ...

2

At DC $\omega = 0$ (all capacitors can be seen as open circuit) we have this situation: simulate this circuit – Schematic created using CircuitLab And $$R_{IN_{DC}} = R_3 + R_4 = 3k\Omega$$ But at high frequency ($\omega = ∞$) when all capacitors can be seen as short circuits we have this situation: simulate this circuit Therefore the input ...

2

Assuming a boost converter power efficiency of about 85%, it needs to take about 1060 watts from the 15 volt supply in order to deliver 30 volts at 30 amps to the load. That means the 15 volt supply will need to deliver about 71 amps.

1

Grouping is usually done for the convenience of someone that is trying to sort a large list of varied items into smaller lists that are easier to navigate. Unfortunately one persons idea of what belongs in what list is often questionable just like in the case of "analog" versus "mixed signal" 1. I have searched many times on a manufacturer or vendor web ...

1

I'd go with controlling the motor with a transistor driven by a PWM signal

1

The pre condition for being in the saturation region is the following: $$V_{GS}-V_{TH} = V_{OV} < V_{DS}$$ By applying only $V_{OV}$ to the gate of $Q_2$ you would be in the threshold between cut-off and linear regions, therefore an additional $V_t$ is applied. Based on that you can say that $Q_2$ is at least conducting. In order to make sure ...

1

$V_{D4} = V_t + V_{OV}$ $V_{G4} = V_t + 2V_{OV}$ $V_{S4} = V_{OV}$ . Hence: $V_{GS4} = V_{G4} - V_{S4} = V_t + 2V_{OV} - V_{OV} = V_t + V_{OV}$ $V_{DS4} = V_{D4} - V_{S4} = V_t + V_{OV} - V_{OV} = V_t$ . Q4 is in saturation if: $V_{DS4} >= V_{GS4} - V_t$ what leads to: $V_t >= V_t + V_{OV} - V_t$ $V_t >= V_{OV}$ . ...

1

Having any energy storing element (inductor or capacitor) implies there is a pole. In-fact, the number of poles is always equal to the number of independent energy storage elements present in the circuit. Thus, this circuit has one pole. For checking the number of zeros, you need to short circuit a capacitor (or open circuit an inductor) and see if the ...

1

For a low-pass or a high-pass simple RC filter, there is always a pole and always a zero. For the low-pass the zero is at infinity i.e. infinite frequency. For high pass, it is at zero frequency (aka DC). But If I simply look at this circuit I would say that there is one pole and no zero If I look at it I see a DC blocking capacitor hence the output ...

1

Use a depletion mode FET to limit the voltage available, simulate this circuit – Schematic created using CircuitLab When the FET's threshold voltage is reached it will pinch off output giving a crude form of voltage regulation. simulate this circuit This arrangement seem to limit at about 2.4V with only a small fraction of a volt drop-out. if you ...

1

The pfet/pnp acting in common emitter mode has a high impedance node which acts with the regulator's load at low load currents (high impedance load) to create an additional low frequency pole which has the potential to cause instability. A capacitor which has an ESR within a particular range is added across the output to add a zero to the loop which cancels ...

1

Some more notes: In order to keep power consumption as low as possible (for an application running 24/7), I increased R1 and R2 to 560 kOhms each, and R3 to 33 kOhms. I further increased R4 to 2k2, and for Q1 I used a BC517 Darlington type. As optocoupler, I used a 4N35, as recommended. This worked quite well, but I also wanted to keep impulses short (for ...

1

I know this is a old post but to benefit anyone that search for the answer that came across this post. The solution is a voltage divider, 220k and 100k resistors will do the job.

1

Any solution that uses a simple counter for incremental encoding suffers a problem: glitching at counter transitions. So, for example, wiring up some '163s to an R-2R DAC will yield a noisy ramp signal. For this reason, encoders that output absolute values (like what's being proposed here) use Gray code. With Gray code only one bit changes at a time. More ...

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