# Tag Info

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ASIC vs FPGA A Field Programmable Gate Array can be seen as the prototyping stage of Application Specific Integrated Circuits: ASICs are very expensive to manufacture, and once it's made there is no going back (as the most expensive fixed cost is the masks [sort of manufacturing "stencil"] and their development). FPGAs are reprogrammable many times, however ...

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Not an expert answer, but some disconnected relevant facts: One of the reasons that ICs often require external passives is that standard silicon ICs are not a good substrate for making capacitors and inductors of significant value on-chip. Thus, a conventional IC, "AS" or not, is not a space-efficient way to put large passives on a board (other than high-...

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If your budget is less then 10-20 thousand dollars (or more realistically 100K+), you have no hope of getting an ASIC made. The common device used instead of an ASIC, in situations where you cannot afford the NRE (non-returnable expenses - basically the cost for producing the masks for etching your asic, as well as the design costs), is to use a FPGA. ...

15

Synthesizing means somehow converting what you have described (in Verilog here) into real hardware. Now in your Verilog you say that you have a 50ns delay. Ok, but now, in term of hardware, how would you convert this into actual hardware? If you are using an FPGA, how would you actually build your 50ns delay using the available FPGA resources (LUT, ...

15

FPGAs can be "re-wired" by re-programming. A FPGA loads it's configuration into it's configurable logic cells when powered. This means it can be re-programmed with no changes to the hardware. ASICs can only be re-wired by modifying the photolitographic masks at the silicon foundry. A microcontroller is a type of ASIC, that executes a program and can do ...

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In large quantities (millions of copies), ASIC can be cheaper than programmable parts. On the other hand, the development of ASIC silicon costs at least an order of magnitude more than development of FPGA or microcontroller (μC) code. The great thing about software is that - almost by definition - it "enjoys rapid prototyping environment" [1]. Silicon ...

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At least from an FPGA standpoint, hard IP refers to features built into the silicon of the FPGA itself. These can range from mixed signal components such as clock management components, PLLs, and high speed serializers and deserializers to fully digital components such as CPU cores, memory controllers, Ethernet MACs, and PCI express cores. Hard cores have ...

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I also read an article that they are used for testing purposes alone. That is so ridiculous that I think you misunderstood the article. FPGAs are used for various applications, including data processing in specialized applications, and as glue logic in low volume applications where developing a fixed function ASIC would not be viable. Open up all kinds of ...

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ASIC means Application Specific Integrated Circuit. If that integrated circuit would contain only passive components then we could still call it an ASIC. Making a silicon die with only passive components is very well possible but there are severe limitations. On an IC capacitors are only practical up to a few nF. Inductors can only be a few nH. Resistors ...

11

Short answer: No. It is not a precedent. There are plenty of Open Source RTLs out there. OpenCores and OpenSPARC are examples, but I know of international academic projects that at the very least were attempting this since the 1990's, almost since the invention of Verilog and before the concept of OpenSource was widespread. The project you pointed to seems ...

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The answer from W5VO tends to focus on the back-end, and this is a major difference between ASIC and FPGA flows; but it misses out the digital design verification part. When getting a design onto silicon can cost a million dollars and more, and you can pack many more usable gates on an ASIC compared to an FPGA, then you spend a lot more time away from the ...

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ASIC means 'Application Specific IC', and that device is very application specific. If you want to build a 4 port Ethernet switch with it, it will do it, and only that. So yes, you need to use the 'ASIC' column for the MTBF figures from your reliability tables. The fact that such figures are next to meaningless for each individual case is irrelevant for ...

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I think the differences can be boiled down into a few key points: First, boards that are designed for ASIC emulation can have several, very large FPGAs that usually provide mostly pure fabric logic resources (as opposed to DSP slices, hard IP cores, and transceivers) with lots of interconnections between them vs. "normal" dev boards which usually have just ...

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Now by end of 2018, a company is working on a platform "Itsy-Chipsy" (assuming a software tools collection plus fab services) to produce two prototype chips for about $400 at a 350x350um size which can fit 14000 gates. If the area size is further divide by 4, down to 170x170um, the cost would be about$100. The \$100 price is based on the pricing of a 2x2mm ...

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It is quite possible to reverse engineer an ASIC and there really isn't much you can do about it. Basically the main way you do it is physically by removing each layer of the ASIC and using a specialized computer program to recover the schematic. It is very difficult to understand all the functions of the ASIC and you can obfuscate it in various ways but ...

8

I would say that there are a couple of different ways that you could argue that. Not sure what the 'best' method is in general, it's going to be dependent on what you're trying to accomplish. It's easy to initialize everything on the FPGA in HDL so that when it comes out of the configuration routine, everything starts from a known state. However, usually ...

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There are so many wrong statements and assumptions that I don't even know where to start. So let's start with my credentials: I have been designing ASICs for 25 years. I have done small, medium and mega chips. (The latter of course as part of a team). ASIC chips are hundreds of times faster than traditional chips. With faster we engineers normally ...

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There are several advantages to this methodology that I can think of: Clock Network - Firstly you only have one clock rather than three. This means that there is less competition for global and local clock routing resources. There are usually only a small number of low-skew clock trees, so minimising usage requirements can help routing. ALM Restrictions - ...

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Short Version There are several methods of cooling below -269°C, but they won't be much use for overclocking a commercial CPU, because coolant temperature isn't everything. Cooling Options Instead of using centigrade, people use Kelvin when talking about very low temperatures. That is becasue there is a minimum possible temperature which can exist, ...

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Porting my answer from SO. Which focuses on why it is impractical to synthesise absolute delays When synthesising clock trees the synthesis tool balances these by adding delays so that all nodes receive the clock at the same time, so it would seem that the synthesis tool does have the ability to add delays. However when ASICs are manufactured there is a ...

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This is a good question, Basically a micro controller and an ASIC have hardware (often referred to as silicon) that is set in stone and can't be changed. An FPGA can be configured to represent many different kinds of hardware (this can include micro controllers). You may think that a micro controller can be made to do many different things but this is all ...

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Liquid Helium is a very poor coolant unless you really want to go to absolute zero. It's heat of vaporization is very low compared to LN2. Reading through the table of the gases, you might find liquid Xenon is better although it is vastly more expensive. Heat of vaporization is important because it means you need to circulate less fluid before it starts ...

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"manufactured ASIC" is a compilation of RTL (which can be open) and particular FAB-supplied libraries of basic elements, and usually third-party I/O pad libraries, for which you need to pay big dollars. These are properties of FAB houses, and they differ in time and evolve with process node. The RTL can be "open sourced", but you need to work hard to ...

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To give a rough idea my network has around one million neurons and ten billion connections. That means ten billion weights. From a NN perspective, this very much sounds like you want to apply L1 regularization to reduce the number of connections; unless you really have good reasons why this needs to be this large, I'm almost certain that you didn't ...

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R-2R is never done, it consumes to much area, it matches extremely poorly, has too high parasitics, etc. etc. Switched capacitor cells and techniques and almost certainly differential design will hold the day. If your process is digital rich and analog light, then a sigma delta approach will give you the right results. "Norsworthy, Steven R., ...

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To answer your question, the same guidelines do not apply to ASICs and gated clocks are used very often to reduce power consumption. In FPGAs, clock signals have dedicated routing resources that ensure low skew delivery of the clocks to fairly large areas of circuitry. If you try to gate the clock then the output of the gate will probably be forced to use ...

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The technology file contains the physical properties of your fabrication process. For example, it would contain the number of metal layers, the design rules, resistances, capacitances, as well as the routing grid needed. This file is specific to the process used, so it would be supplied by the foundry or your gate library vendor. If there are multiple ...

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I'd like to expand a bit on Nick's (great) answer. Yes, the cost of production is usually the most important parameter of all, but, even assuming that you could design ASICs at the same cost as, say, FPGAs, this still wouldn't lead to a much wider adoption of ASICs. The issue here is the fact that there are very few ASICs' manufacturers, and they are very ...

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Why not look for a generally available existing crypto IC that does what you want? Example family of secure authentication ICs using the SHA-256 hash algorithm with a 256-bit key length There are development kits. Sparkfun produce a breakout for it. It communicates using I2C or 1-wire. (caveat - I've no idea if this particular chip can be used ...

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