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3 votes

What/why are the patterns in the "unused" portion of this ASIC?

I'm not an ASIC designer, but on a quick search found What is the use of adding filler cells to a design? which contains answers such as the following which sound reasonable. I.e. to meet the ...
Chester Gillon's user avatar
2 votes

How to do clock signal rising edge detection in Chisel (scala)?

In your code, the compilation errors you are encountering are due to an incorrect cast. You are trying to use Clock variables as if they were ...
porrokynoa's user avatar

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