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10

It means that the current for charging the Base is the same as the current used to discharge the Base capacitance when they do fall time testing. An exemplary circuit to do so is shown in this datasheet. You may also have a look at: How to determine BJT switching time


7

You should just plug this circuit topology into circuit simulator and start experimenting to figure out on your own how these work. This way you will learn the most. These circuits use one transistor as a constant current circuit (sinking in your left circuit / sourcing in the right circuit) to linearly discharge / charge the capacitor. The other transistor ...


4

The two circuits are both based on emitter followers. As you may recall, the emitter follower has a gain of about 1 and an offset of one base-emitter voltage, Vbe. The followers are arranged as a complementary pair. In both cases the purpose of the diodes D1 and D2 is to insert a bias that parallels the Vbe of each transistor. (Vbe is about the same as a ...


3

You are missing one value in your picture. Voltage between base and collector (Vbc, which is actually opposite to Vce). Do you already see that there is no miracle? Even without deep knowledge of PN junctions, just elementary circuit laws (like Kirchhoff's Laws). Vce=Vbe-Vbc


3

For an individual NPN bipolar junction transistor (BJT), the condition for saturation is $$ V_E < V_B > V_C $$ i.e., the transistor's base-emitter diode AND its base-collector diode must both be forward biased. Applying Kirchoff's voltage law to the Darlington pair (fig. 1) we see that the voltage at its collector is $$ V_{Q2.C} = V_{Q2.E} + V_{Q2....


2

I don't understand why I can apply a voltage divider in the 30K and 20K resistors since the base is connected between them. The emitter resistor of 1 kohm projects an impedance onto the base that is beta times higher. So, if beta is 100 and the emitter resistor is 1 kohm, the base will look like a loading impedance of 100 kohm. This loading resistance is ...


2

Michael's simulation already provided a detailed view on the circuit. To quickly answer the question regarding the component calculations: R1 and R2 form a voltage divider which determines, after Vbe drop, the voltage on R3, forming the constant current to charge the capacitor (charge circuit on the right, discharge on the left). R1||R2 should be low ...


2

Even if Vce1= 0 V and Ic is low, Vce2 cannot be less than Vbe2 which is not fully saturated as a single transistor can be, yet hFE will be reduced. Therefore other configurations can be used. simulate this circuit – Schematic created using CircuitLab Therefore you may say... ...that the Darlington transistor, as a switch, adds a diode drop ...


1

You're interpreting the operation of the current source wrongly. For the current source to provide a current of \$g_mV_{\pi}\$ (or any current, for that matter) into a \$0\small \:\Omega\$ load it must have \$0\$ V across it. If it were supplying a load other than \$0\small \:\Omega\$, it would have a voltage other than \$0\$ V across it. Your equation is ...


1

What happens INSIDE a current sink is what allows the zero Ohm link to simply carry the current generated with the internal potential. In any circuit that you deal with you would have no problem with the concept of current flowing in an ideal zero Ohm wire - having the current provided by a current source should not make any difference. Imagine a high ...


1

You are making an incorrect assumption. Specifically, you are assuming that if there is current flowing through the current source then there must be a voltage across that source. This is not correct. The voltage across a current source is not determined by the current flowing through it; the voltage across a current source is determined by the rest of the ...


1

There's no contradiction if you're using the model for what's it's intended for. The hybrid pi model is only useful for the dynamic gain of the transistor (and then at only one specific emitter current), not about the static biassing. If you want a model for the static biassing, then a more useful one is to replace the input resistor with a diode, and the ...


1

I have 2 images above. The first one is Ic vs Vce which i captured in a lab at university. The second I took off the internet of a FET because i didnt have one. In the FET one you can see that all the curves split off before they come flat. Giving a R = V/I for those curves will give different resistances. However, in my BJT one, you can see that before the ...


1

If you assume that the opamp is a rail-to-rail device you can then say from inspection: The configuration has unity gain. At zero load current the output limits at approximately +/- 4.3V (one V(be) drop from each supply). The configuration will clip at approximately +/-70mA and the output voltage will reduce linearly (the 10 Ohm resistor) above that current....


1

simulate this circuit – Schematic created using CircuitLab This is Common Emitter design, H bias with negative feedback design, not perfect for every variation on Rin,Rout, gain and V+ , but one that closer matches what you were trying to do with up to 50x more voltage gain. ( assuming you meant to show Rc on V+ but didn't know how to use editor.) ...


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