OFDM isn't a modulation technique. It stands for "Orthogonal frequency-division multiplexing" and is a way of splitting the spectrum into discrete channels for sending data. Each of those channels, which is just a single frequency carrier in its own right, requires the data to be modulated onto it. In this example BPSK is used.
Jotorious is right. However, based on information from AD8347 datasheet this chip is based on classic Costas loop circuit with multipliers as phase-detectors. So for the carrier tracking step you should use Costas loop instead of squaring loop.
Your received signal has several deterministic but unknown parameters, the amplitude, the frequency offset, and the sampling timing offset, and perhaps some others. At a minimum you need an AGC to get to a known and desired amplitude, a carrier recovery circuit ( costas loop or a gardner loop) and a symbol timing recovery circuit (early-late gate combined ...
For a project of mine(uhf radios, pic32mx450f), I went with bpsk and 8b/10b encoding, with a 10 sine + 8b/10b k_28_1 preamble. This allows syncing to the correct phase, and then I run the moving bitstream through the detector until it hits the special code.
For phase detection, I looked at quite a few different ways, but ended up doing simple peak ...
Most 40,000 Hz piezo transducers are high-Q, which means that once you get them oscillating, changing amplitude or phase takes awhile. Or it requires an extremely large transient. My measurements of a cheap piezo transducer revealed an equivalent circuit like this:
simulate this circuit – Schematic created using CircuitLab
The components L1, C1, and ...
You're getting nothing wrong. This just looks like your receiver isn't perfectly using the same frequency as the transmitter.
A frequency offset is just a phase that is a linear function over time – hence the rotation in the constellation diagram.
Also, you've got some I and Q offset. This should be rotationally symmetrical to 0+0j.
For the system you have drawn (with no possible way to judge which channel is correct) if one is in error then, the probability for system error has doubled. The above is based on the confusing symbol where the two channels are recombined. I initially read it as a multiplier.
If the symbol is an adder then two BPSK signals can add and produce double the ...
For 0/180, if you track the carrier (RF, IF) phase, you'll only need a single-phase local-phase reference.
For +60/-60, for optimal BER you'll need inphase and quadrature, so you set up matched filters with precise phasing. Keep in mind these are not orthogonal symbols.
It appears the SNR from your simulation is 3 dB too low. Since you are working in MATLAB, it is easy to check. Look the values of h, s, n, and Eb_N0_db and make sure you have scaled them all correctly.
1) The reference clock can go as fast or as slow as you like. Most FPGAs have built-in PLLs that can convert an external reference clock into whatever frequency you need (within reason). So you could take an external 10 MHz reference and multiply it up to 100, 150, 200 MHz, etc.
2) No, FPGAs do not contain DACs. It may be possible to build an R-2R DAC, ...
Partially you question is answered in this topic. Probably you need analogue carrier recovery circuit, for example Costas loop-based circuit. Good theoretical review of BPSK Costas loops is given in this article.
The AWGN channel with noise power spectral density
And the signals:
In a normal coherent oscillator, you would receive something like the following in the constellation diagram (noise not represented):
(the picture may be wrong because of ...
1.414 is the square root of 2. If the same signal is sent over the 2 independent channels, then your received Noise PSD is the same, but your signal is now twice as powered. You add the signals, but the noise is not additive because it is IID / uncorrelated. Twice as much power is a 3dB Gain. I'm a little hazy on BER curves, but if that Q(sqrt(g)) is the ...