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69

Your calculations are correct in essence. For a 1440p60Hz signal, you have a data rate of 5.8Gbps once you allow for blanking time as well (non-visible pixel border in the image output). For HDMI/DVI, a 10/8b encoding is used, which means effectively although you have say 24bit of colour data per pixel, actually 30bit is sent as the data is encoded and ...


43

The approach which you show is quite an old topology for motherboards - it predates PCIe which really puts it back somewhere in the '00s. The reason is primarily due to difficulties of integration. Basically 15 years ago the technology to integrate everything onto a single die was virtually non-existent from a commercial standpoint, and doing so was ...


22

Welcome to the biggest challenge with half-duplex communications systems. RS-485 is not a protocol, it's a standard which defines the electrical properties for a half-duplex(*) differential link. There is nothing in the specification about how data is to be sent over that link, or in fact how the link is used. As such RS-485 transceivers have no automatic ...


19

Modern computers are surprisingly fast. People will happily load up full HD 30fps videos without realising that that involves billions of arithmetic operations per second. Gamers tend to be slightly more aware of this; a GTX 1060 will give you 4.4 TFLOPS (trillion floating point operations per second). Please explain if my calculations are wrong and how ...


16

Nets connect two or more pins together - the connected pins should be routed in copper. In Eagle, buses don't actually do very much, they just look pretty. You can however use them to keep track of which net names you a trying to route from one side of a schematic to another. Here is an example of a few Eagle buses. Basically rather than drawing individual ...


15

Look closer... There is only a single pair of pull-up resistors for each bus. Your diagram shows four separate I2C buses. The multiplexer and the repeater isolates the segments. Thus, since you only have one bus, you only need two resistors: One for SCL and one for SDA.


14

When the 1MB of memory is referred to, do the books refer to the ROM and RAM of the computer. Is the ROM + RAM = 1MB of memory interfaced? Correct. The CPU does not distinguish between RAM and ROM; the 1 MB address space is shared between both. If yes, when memory mapped I/O is shown as a memory segment in this 1MB memory space.....do they mean that the ...


13

I would use Net Labels to connect buses together. Ports are mostly used when connecting nets from different sheets. As The Photon says, the 8 signals from the left IC must have the same net label as the 8 signals from the right IC. Your bus connection should look like this: Buses are used to graphically represent how a group of related signals, such ...


12

Dominant is 0. Recessive is 1. Dominant applies to 0 because if two arbitration ID's are being transmitted at the same time and the first 4 bits are the same and the fifth is 0 for one of them and 1 for the other, the ID with the 0 will end up being transmitted. Transmission of the message with the larger arbitration ID will be tried again after the other ...


11

The link between display card and LCD panel is carried over several high-speed differential pairs using TMDS signaling, usually called "lanes". Typically four lanes are used, so one can say that the bus is 4-bit wide. For some more details there is a stackhexchange answer. Each LCD panel model is usually produced with several interface incarnations, so one ...


10

The CU (Control Unit) is responsible for all data transport to and from the ALU. The ALU doesn't see buses, it sees two N-bit wide inputs, and ditto output. The CU must make sure that both inputs of the ALU are loaded (latches) with the required data. When the ALU has performed the operation the CU will route the output via internal (and possibly external) ...


10

In addition to the perfectly accurate answer given elsewhere, it may also be useful to consider the lower level meanings of the phrases dominant and recessive. In both CAN and LIN at the physical layer the bus "floats" to a particular state when no nodes are communicating. This is the recessive state. Any node which drives a dominant bit will override this ...


10

You're forgetting a couple of important facts: A flip-flop isn't a single atomic gate, but made up of multiple gates. It takes time for a signal to pass through a gate (or propagate). There is no such thing as a pure square wave. Take this diagram of a transparent latch: Assume each gate requires one "time unit" to propagate the signal. The D signal ...


10

Well, I spent a solid hour or so trying to find the answer, gave up and asked here. Then a few minutes later I had the idea of seeing what shortcuts are available during routing (Ctrl-F1) and then finding that the 5 key will go through via patterns, one of which is the pattern I was looking for. So, pressing 5 while routing multiple net's will give you ...


10

From a professional point of view, this is a critical problem. Missing termination will cause energy bouncing back at the end which isn't terminated. This could lead to strange random noise on the line, such as for example transients or random pulses that seem like ok binary pulses, but with wrong voltage levels etc. CAN Hi and Lo don't necessarily behave ...


9

The W65C21 PIA (Parallel Interface Adapter), also made by Western Design Center (WDC) along with the W65C02S, is a parallel GPIO chip specifically designed to work with the address/data/clock interface of the 65xx series of chips. (The 6521 is patterned after the 6821 PIA that was designed by Motorola to go with the 6800 microprocessor). You may also see ...


9

I can't say I'm an expert in a computer architecture, but I'll take a shot at answering your questions. This looks to be the typical layout of motherboards. As Tom mentioned, this is no longer true. Most modern CPUs have an integrated northbridge. The southbridge is typically either integrated or made unnecessary by new architecture; Intel's chipsets "...


9

It's very similar to radio communication of the military or the police. A protocol is required. Master slave is easy and good for most cases. But another option is to do it like humans do: Listen. If someone speaks- wait. If you think no one speaks- you can speak. Wait for confirmation. If no confirmation received- speak again. If you want to broadcast,...


8

As you guessed, at 20 MHz you will have no problem designing with 90 degree bends. You probably don't even need to worry about setting up your trace geometry to obtain a controlled-impedance microstrip or stripline. If you were designing at 50 MHz or higher, you would probably want to design with a trace geometry that gives a roughly controlled ...


8

Here is a little overview on chip internal buses, which are suitable for FPGAs: Advanced Microcontroller Bus Architecture (AMBA) from ARM Ltd. Current version: 5 Specifications Further reading: Wikipedia Commonly known buses in that family: Adavance Peripherial Bus (APB) Advanced High-performance Bus Advanced Extensible Interface (AXI) Variants: AXI-Lite, ...


8

It sounds like you want an octal buffer with tri-state output. For your 5 V application, a device such as a 74HCT245 will do it.


8

In order to capture all the information you need to sample at at least twice the highest frequency component in the input signal. If you do a PSD plot of the input you'll see that there is significant power at higher than 400kHz. You might have to sample at 8MHz to get most of it. Also, generally you will want to precede the ADC with an ANALOG low pass ...


7

A wire can be a bus if it is a serial link carrying many individual pieces of information. More usually, a bus is regarded as a collection of wires that transport digital information from A to B. 64 bit processors (PCs etc.) have a 64 bit-wide bus between the CPU and their memory chips and possibly to other devices. It doesn't have to be inside a computer ...


7

First, download 8086 datasheet for reference. When the 1MB of memory is referred to, do the books refer to the ROM and RAM of the computer. They refer to the addressable space of the microprocessor. Look into datasheet, it shows A19:A16 and AD15:AD0 lines which are used for addressing outer space during T1 cycle. CPU does not care what is there in the ...


7

Typically the situation was avoided by the outputs being open-collector instead of tristate, with a pullup resistor to +5V completing the circuit. If one device drove the shared line low and the other went open-collector, the shared line would stay low. If there was only a conflict for a very short time, this would cause no problems at all. For a ...


7

For off-board components I use a suitable footprint (connector or group of pads) to provide the connection points, and use that footprint name in the schematic, rather than the actual component footprint. This substitute footprint need not match the component pin layout, as long as the footprint pin numbers match the schematic symbol pin numbers.


7

As with many texts written for beginners the situation has been somewhat simplified. The assumption is that a 32-bit processor does all address operations and calculations also in 32 bits. From that it assumes a 32-bit address bus. Therefore the maximum address range is 4GBytes. That same reasoning is then extended to a 64-bit processor. In real life it ...


6

Turns out I missed a crucial detail in the accompanying text, and the registers are indeed composed out of two (master-slave) sub-registers: The Use of Master–Slave Registers Note that the contents of the PC are incremented within the same clock pulse. As a direct consequence, the PC must be implemented as a master–slave flip–flop; one that ...


6

Yes, there may be physical damage. The longer the situation persists, the more the chance for damage. In case this is a problem you foresee happening often in your setup, you should probably work out a better scheme, or at the very least include a series resistor in each of the data lines. The resistor should be chosen such that in the worst case (both sides ...


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