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70 votes
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How does my screen driver handle so much data?

Your calculations are correct in essence. For a 1440p60Hz signal, you have a data rate of 5.8Gbps once you allow for blanking time as well (non-visible pixel border in the image output). For HDMI/DVI,...
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43 votes

Why do CPU's typically connect to only one bus?

The approach which you show is quite an old topology for motherboards - it predates PCIe which really puts it back somewhere in the '00s. The reason is primarily due to difficulties of integration. ...
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23 votes

How to find the UART line is free for send data

Welcome to the biggest challenge with half-duplex communications systems. RS-485 is not a protocol, it's a standard which defines the electrical properties for a half-duplex(*) differential link. ...
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20 votes

How does my screen driver handle so much data?

Modern computers are surprisingly fast. People will happily load up full HD 30fps videos without realising that that involves billions of arithmetic operations per second. Gamers tend to be slightly ...
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18 votes

Difference between buses and nets

Nets connect two or more pins together - the connected pins should be routed in copper. In Eagle, buses don't actually do very much, they just look pretty. You can however use them to keep track of ...
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17 votes

How does an Intel processor "talk" to an I2C device?

So far I understand, Intel processors use specialized CPU instructions (IN/OUT) to communicate with peripherals. Uh, this might have been true in the 1970s and 1980s, but really wouldn't even be ...
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16 votes
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How many pull up resistors per I2C bus

Look closer... There is only a single pair of pull-up resistors for each bus. Your diagram shows four separate I2C buses. The multiplexer and the repeater isolates the segments. Thus, since you only ...
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15 votes
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Does ISA bus (or PC/XT bus) have some means of arbitration to resolve bus contention?

PC and XT The original IBM PC simply extended the Intel chipset bus to connectors using buffer drivers. The clock rate on the card bus was the exact same as the clock rate used for a CPU cycle. So ...
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14 votes

How does an Intel processor "talk" to an I2C device?

An Intel Core processor is attached with Direct Media Interface DMI to the Platform Controller Hub PCH. The PCH contains all peripherals, like PCI, USB, AHCI, Display outputs all the stuff. But ...
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13 votes
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What exactly is "dominant" and "recessive"?

Dominant is 0. Recessive is 1. Dominant applies to 0 because if two arbitration ID's are being transmitted at the same time and the first 4 bits are the same and the fifth is 0 for one of them and 1 ...
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  • 285
12 votes

Are there any standard FPGA internal buses?

Here is a little overview on chip internal buses, which are suitable for FPGAs: Advanced Microcontroller Bus Architecture (AMBA) from ARM Ltd. Current version: 5 Specifications Further reading: ...
11 votes

What exactly is "dominant" and "recessive"?

In addition to the perfectly accurate answer given elsewhere, it may also be useful to consider the lower level meanings of the phrases dominant and recessive. In both CAN and LIN at the physical ...
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11 votes
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Setup Time, Hold Time - What is the underlying principle for having them?

You're forgetting a couple of important facts: A flip-flop isn't a single atomic gate, but made up of multiple gates. It takes time for a signal to pass through a gate (or propagate). There is no ...
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11 votes

How does my screen driver handle so much data?

The link between display card and LCD panel is carried over several high-speed differential pairs using TMDS signaling, usually called "lanes". Typically four lanes are used, so one can say that the ...
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11 votes
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The CAN bus in this vehicle has only one 120 ohm termination resistance. What problems would this provoke?

From a professional point of view, this is a critical problem. Missing termination will cause energy bouncing back at the end which isn't terminated. This could lead to strange random noise on the ...
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10 votes
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Can Altium do via stitch patterns when interactive routing a group?

Well, I spent a solid hour or so trying to find the answer, gave up and asked here. Then a few minutes later I had the idea of seeing what shortcuts are available during routing (Ctrl-F1) and then ...
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  • 1,060
10 votes

Sampling rate understanding for ADC requirement

In order to capture all the information you need to sample at at least twice the highest frequency component in the input signal. If you do a PSD plot of the input you'll see that there is ...
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9 votes
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Is there a GPIO IC that has a parallel interface?

The W65C21 PIA (Parallel Interface Adapter), also made by Western Design Center (WDC) along with the W65C02S, is a parallel GPIO chip specifically designed to work with the address/data/clock ...
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  • 47k
9 votes

Why do CPU's typically connect to only one bus?

I can't say I'm an expert in a computer architecture, but I'll take a shot at answering your questions. This looks to be the typical layout of motherboards. As Tom mentioned, this is no longer ...
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  • 8,454
9 votes

Does ISA bus (or PC/XT bus) have some means of arbitration to resolve bus contention?

No there is no sanity check for addresses. If you set two or more cards to same address, they all get written with same data. Reading will cause a conflict where one card pulls low and another high. ...
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8 votes
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SPI Bus Termination Issue

It's difficult to answer this without all the details, but here is a generic look at the problem which I believe may also be the more useful type of answer for this site. Multi-node-nets should ...
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8 votes

Looking for a device to "pass through" or "make high impedance" 8 bits based on one control bit

It sounds like you want an octal buffer with tri-state output. For your 5 V application, a device such as a 74HCT245 will do it.
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  • 17.9k
8 votes

Is there any viable DIY method of fusing 2 (or any amount of) cables together to form ribbon cable?

You can either: Twist the cables together, for example with a drill, twisted enough they won't come apart. Check some youtube videos. That is the best because for differential buses like CAN, RS485, ...
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  • 7,575
7 votes
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STM32: avoiding DMA & CPU collisions

What this means is that if the DMA and CPU are both targeting RAM, depending on whose turn it is in the bus matrix scheduler, the CPU may be forced to wait for the DMA's turn to be finished. e.g. If ...
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  • 2,371
7 votes

Memory interfacing with 8086

First, download 8086 datasheet for reference. When the 1MB of memory is referred to, do the books refer to the ROM and RAM of the computer. They refer to the addressable space of the ...
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  • 6,570
7 votes

Will multiple chips outputing onto a bus for a few nanoseconds cause damage?

Typically the situation was avoided by the outputs being open-collector instead of tristate, with a pullup resistor to +5V completing the circuit. If one device drove the shared line low and the ...
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7 votes

Guidelines on PCB design with components only partially wired on PCB traces

For off-board components I use a suitable footprint (connector or group of pads) to provide the connection points, and use that footprint name in the schematic, rather than the actual component ...
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7 votes
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Microprocessor architecture bits vs bus sizes

As with many texts written for beginners the situation has been somewhat simplified. The assumption is that a 32-bit processor does all address operations and calculations also in 32 bits. From that ...
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