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4

As FPGAs* do NOT support on-chip tri-state drivers you can not implement option-1 on them. You should go for the MUX version. *At least I don't know any FPGA of reasonable size which still has them.


0

I2C is a communication protocol that operates over two wires. Voltage sequencing over those wires communicates between the I2C master (controlled by software) and an I2C slave (perhaps a temperature sensor). Software does not usually directly manipulate the voltage sequencing of the wires of I2C (that would be called "bit banging"), but instead convinces ...


14

An Intel Core processor is attached with Direct Media Interface DMI to the Platform Controller Hub PCH. The PCH contains all peripherals, like PCI, USB, AHCI, Display outputs all the stuff. But also the SMBus (I2C) interface, which connects all the little sensors together. The PCH makes these peripherals available in the address space via the DMI. This ...


15

So far I understand, Intel processors use specialized CPU instructions (IN/OUT) to communicate with peripherals. Uh, this might have been true in the 1970s and 1980s, but really wouldn't even be very useful for an I²C peripheral, and incredibly intrusive for the programming of the CPU. So, instead, there's some peripherals attached to a much, much faster ...


4

i just looked randomly at one datasheet of Intel Processor [EDIT:] its a on-package Platform Controller Hub (PCH) datasheet in the introduction: and you also might see it sometimes under different name: (SMBus) your question, how it looks like this is really good tutorial that explains it: https://learn.sparkfun.com/tutorials/i2c/all its just like this:...


2

PCs have several I²C controllers. Most prominently those for the DDC and those for the RAM modules' SPD. Sometimes temperature sensors and fan control is also put on I²C buses. It depends on the board's chipset how to control those I²C buses. Most host adapters are very simple and consist of not much more than a clock generator, a shift register and some ...


1

The key to getting a multidrop interface to work, like this one in the OP's post, is to manage the lengths of the unterminated stubs. They are the "vertical" connections that come off the main signal lines and go the line receivers on the bottom. How long they can be without compromising signal integrity depends on the edge rate of the signals. An RS-422 ...


1

Those diagrams are like schematics, they are correct but missing actual wiring details. The bus could be 100 meters long, and the branches where to put a receiver might be only few millimeter stubs, so regarding the electrical signal they really are not branches at all when the receivers are just in-lined on the bus. And the termination resistor must be at ...


4

When you send a high speed signal down a cable, the current that initially flows is dictated by the voltage applied AND the characteristic impedance of the cable. For the types of cable recommended for RS485 and RS422, the cable characteristic impedance is circa 100 ohms. So if 1 volt is applied at the sending end an initial current of 10 mA flows and all ...


1

To avoid reflections which mess the signal unreadable matched load is needed at the receiving end of the line.Bidirectional (=half duplex only, no more than one talker at a time) traffic needs matched load at the both ends of the line. The receiver in the RS422 or RS485 IC doesn't be the needed load, the voltage sensing circuit takes very little current ...


1

Has nothing to do with cpus, memory, etc. For PCIe you are either a root complex or an endpoint. As wikipedia points out and as would other places (many good resources out there) there is one root complex and the rest are endpoints. All point to point connections (through bridges as needed) to the root complex. Once enumerated typically the root complex ...


-1

To answer your question simply and accurately, there is no arbitration on the PC/XT bus. If you do an I/O or memory read and there are more than one adapters with the same address, both will drive the bus with their respective data. As to damage, I can't remember ever damaging a card or motherboard and I configured and built dozens of PC/XT computers and ...


0

The "root complex" is a logical construct that consists of the CPU, system memory, and PCIe root ports. So all CPU<->memory operations take place within the root complex. And that also means that components within the root complex have to direct accesses to addresses that correspond to the PCIe bus out over PCIe root ports, as well as terminating PCIe ...


2

There was an almost ghostly effect to be observed on 1980s computers with multiplexed address/data buses - reading from addresses where there was no device at all tended to give you what looked like an ASCII table in a debugger. What likely really happened was that you read back the capacitive charge remaining from the address writes.... feasible if there ...


14

PC and XT The original IBM PC simply extended the Intel chipset bus to connectors using buffer drivers. The clock rate on the card bus was the exact same as the clock rate used for a CPU cycle. So with approximately \$4.77\:\text{MHz}\$ (derived by dividing by 3 a \$14.31818\:\text{MHz}\pm 5\:\text{ppm}\$ crystal rate) on the PC's CPU, this meant that a ...


0

In general, for any computerized communications scheme, end points need to have unique addresses. Telephones (or at least telephone lines for landlines) have unique phone numbers, computers have unique MAC addresses (and get assigned unique Ethernet addresses, or all h*** breaks loose), etc. So in general, not just for ISA and PCI, endpoints have unique ...


4

There is no mechanism to prevent more than one card from responding to an address from the bus master. It is not a significant issue and I don't know of any computer buses that had such a mechanism. Even if multiple cards did get enabled simultaneously the chance of damage is very low and the buffer devices are usually designed to survive such shorts. ...


9

No there is no sanity check for addresses. If you set two or more cards to same address, they all get written with same data. Reading will cause a conflict where one card pulls low and another high. But it mainly uses LSTTL era chips where the chips can survive this, and the period/duty of the conflicting read is so short.


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