12 votes
Accepted

gray code clock domain crossing FIFO fast to slow

In an asynchronous FIFO, one clock domain is associated with the write port, and the "head" pointer (the next write address) is kept in that clock domain. Similarly, the other clock domain ...
Dave Tweed's user avatar
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10 votes

How does 2-ff synchronizer ensure proper synchonization?

The simple answer is that they don't on their own. The synchroniser is there not to ensure the data gets across, but the ensure you don't end up with metastable signals feeding lots of other signals ...
Tom Carpenter's user avatar
6 votes
Accepted

How to calculate the number of required flip-flop stages needed for clock-domain crossing?

The number of flip flops needed depends on three things: target MTBF requirement clock rate ‘crunchiness’ of the flip flops The latter point, ‘crunchiness’, is also called metastable hardness, and ...
hacktastical's user avatar
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5 votes
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Why double synchronizer alone is not enough for multi byte transfer between two clock domains?

Transferring a single bit is simple. It has only two states, and when a transition occurs, it can only be either in the previous state or the new state. Therefore the ONLY concern is metastability, ...
Dave Tweed's user avatar
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4 votes
Accepted

Distinguishing clock domains in designs

First part of the answer: Clocks coming from the same oscillator and produced in an internal PLL have a known phase relation. The tools know this and do check that transfers from one of these clocks ...
asdfex's user avatar
  • 2,729
4 votes
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Clock Domain Crossing for Pulse and Level Signal

You can add an edge-detection to the pulse/strobe synchronizer. How does a normal pulse/strobe synchronizer work? If it supports a busy signal, then the input is blocked until the circuit is ready ...
Paebbels's user avatar
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4 votes
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questions about up-sampling and moving from slow to fast clock domain in FPGA

So the first question I want to ask, How would you move the data stream from the slow to fast clock domain? I already made a working mechanism for this, I filled up a FIFO (with 1024 depth) and right ...
Marcus Müller's user avatar
4 votes

Why do we use a gray encoded signal by 2 stage flip-flop in asynchronous FIFO to avoid race-condition issue?

Obviously, the slow side of the FIFO is not going to see every state of the fast-side counter when it is counting at full speed. Fortunately, with proper design, such as using Gray code to transfer ...
Dave Tweed's user avatar
  • 173k
3 votes

Syntax and/or best practice for buffering a vector in Verilog or VHDL

A FIFO will work in most if not all scenarios, but it is not the only solution for multi-bit clock domain crossing. Since the source data rate is low in your scenario when compared to the destination ...
scary_jeff's user avatar
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3 votes
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Clock Dividers with Clock Domain Crossing

Depends on your vendor On most modern FPGA's of the two biggest vendors, your first assumption is correct and you won't need synchronization registers for the CDC if your clock divider is written ...
DonFusili's user avatar
  • 1,067
3 votes

Metastability error propagation with flip flop

The first FF is not always metastable. Assuming that input edges are uniformly distributed with respect to its clock, the first FF has a certain probability of going metastable that is related to the ...
Dave Tweed's user avatar
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3 votes

Maximum data rate that can be achieved between PIC and FPGA

I suggest you look at using the PIC24F DMA controller to transfer SPI data directly into RAM. You'll have to read the datasheet to figure out what data rates are possible.
Spehro Pefhany's user avatar
3 votes
Accepted

Clock domain crossing between OV7670 interface and AXI4-Stream

Asynchronous FIFO Asynchronous FIFO is an ideal approach to consider implementing between for crossing data safely across the two clock domains. If you are doing this in Vivado, I suggest you use the ...
Mitu Raj's user avatar
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3 votes

Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?

It seems you've heard of metastability calculations. If so, you've probably noticed the part about a mean-time-between-failure dependence on four parameters (metastability resolution time, ...
V.V.T's user avatar
  • 4,242
3 votes

STM32 USB virtual port data sending problem

The function is defined as: uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) So you can send anything you want in binary form: ...
out0f0rder's user avatar
3 votes

STM32 USB Full Speed and card reading causes slow USB speed

I cant use hardware because of some limitation You can't have your cake and eat it too. The software only reads the card at the lower speed. Nothing to do with USB. Maybe use a better MCU if the one ...
Kuba hasn't forgotten Monica's user avatar
2 votes
Accepted

What will the output of filp-flop if its input is metastable?

In the paper it is explained that metastability is inevitable in a system with asynchronous signals: In a multi-clock design, metastability cannot be avoided, but the detrimental effects of ...
Vicente Cunha's user avatar
2 votes

SDC constraints for two flop sychronizer

A two flip-flop synchronizes can be constrained with the follwing XDC lines. XDC is a Xilinx flavor for the commonly known Synopsis Design Constraint files (SDC). ...
Paebbels's user avatar
  • 3,927
2 votes

Clock Domain Crossing for Pulse and Level Signal

Depends on what information about the signal is important. If you have something that can be either a relatively constant level as well as relatively short pulses that are closely spaced, then what ...
alex.forencich's user avatar
2 votes
Accepted

Crossing independent domain clocks (slow to fast)

You can never expect 100% reliability, but you can expect 99.99999...% reliability. As you can see in the picture below (from here), the MTBF is proportional to the clock frequency and number of ...
crj11's user avatar
  • 5,576
2 votes
Accepted

possible clock domain crossing?

This looks like a 54 MHz circuit, since you have no obvious control of the phasing of the two clocks. So long as the two clocks are synchronous, and all of the clk_27 to clk_54 paths are timed for 54 ...
Sean Houlihane's user avatar
2 votes

Asynchronous FIFO cdc question

1) Why there is no multi-bit synchronization problem for slow clock domain ? The point with a gray counter is that if only one bit changes at a time, you can either see the old value or the new value,...
asdfex's user avatar
  • 2,729
2 votes

Can I use 2 Flop synchronizer to migrate a pulse from one clock domain to another provided that clocks phase shifted but of same frequency?

The issue is how much they're out of phase. If the data can change during the FF's setup and hold times you have a metastability problem and need to use 2 FFs: the second will be clocked when any ...
toiler's user avatar
  • 59
2 votes

Clock domain cross and metastablilty problem

Yes, if the metastable state occurs, it is equally likely to resolve to either 0 or 1. This really doesn't matter in the grand scheme of things, however. Let's say that the asynchronous input makes a ...
Dave Tweed's user avatar
  • 173k
2 votes

Clock Domain Crossing

A chain of flip-flops does not 'cure' metastability. However, by delaying the final decision, it gives more time for the metastability to resolve itself, so reduces its likelihood. As the likelihood ...
Neil_UK's user avatar
  • 167k
2 votes

Clock Dividers with Clock Domain Crossing

Yes, it's all one clock domain as far as synthesis is concerned. You can draw a circle around all three modules, and there's only on clock entering that circle. The fact that some of the logic inside ...
Dave Tweed's user avatar
  • 173k
2 votes

Asynchronous FIFO for fast-write-slow-read

If the average input and output data rates are fixed and different, then you will overflow or underflow a FIFO eventually. There is no 'processing' you can use to avoid corrupting data. What a FIFO ...
Neil_UK's user avatar
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