60
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How is 255 Tbit/s processed in optical fiber communication?
It seems like you're referring specifically to http://www.nature.com/nphoton/journal/v8/n11/full/nphoton.2014.243.html . It can be read here: https://www.researchgate.net/publication/269099858_Ultra-...
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43
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How is 255 Tbit/s processed in optical fiber communication?
Rather than worrying about a research paper that's pushing things to the limit first start by understanding the stuff sitting in front of you.
How does an SATA 3 hard drive in a home computer put 6 ...
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41
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How does the current processor technology with low clock rates (<10 GHz) deals with mmWave (>10 GHz) technology used in 5G?
So, how do processors deal with the frequencies in the range of 20-100 GHz?
They don't.
Even if we consider a demodulation of data to lower frequencies from carrier frequencies, there needs to be a ...
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37
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How to communicate faster than the system clock
I guess the confusion is you assume you can only send one bit per clock cycle. There are lots of ways a communication scheme can essentially encode more than one bit per symbol. A symbol is abstract ...
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32
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How can you achieve decent clock accuracy in microcontrollers (e.g., max 1 second drift in a year)? How do digital watch manufacturers accomplish it?
Have you tried comparing with what accuracy you actually get from a digital watch? I don't remember them delivering "1 second per year" accuracy.
The crystal you linked was 50ppm. The ones ...
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19
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Why are DIMMs not equipped with a heat sink like a CPU?
You're assuming that the power dissipation is directly related to the clock rate. That's true but there's more.
Suppose I have this chip A where only 10% of the chip area (die size) runs at the ...
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15
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How is 255 Tbit/s processed in optical fiber communication?
Ignoring the details of the specific transmission in question (which @alex.forencich has already discussed in considerable detail), it seems like it's probably useful to consider the more general case....
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14
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HSI and MSI - Applications of two Internal RC OSC in Microcontroller
HSI is way more accurate, while being less flexible.
Looking at the highlighted values in the datasheet, MSI frequency becomes extremely unreliable at the lower ends of the temperature and the supply ...
14
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Is there a small (6-pin) DIP I can use to generate multi-MHz squarewave clocks with an external crystal?
The LTC1799 can be programmed by a resistor and a link to produce a vast array of frequencies.
Is there a small (6-pin) DIP I can use to generate multi-MHz
squarewave clocks with an external ...
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13
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Why are DIMMs not equipped with a heat sink like a CPU?
DIMMs don't dissipate the same power a CPU does, so they don't need the same cooling. In addition, the power the memory and control chips do dissipate is much more spread out physically.
Power ...
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12
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What kind of use cases require a 2GHz, 4GHz, 6GHz, 30GHz or 100GHz oscilloscope?
Systems where you needed to debug, test and validate things that operate at high frequencies would require scopes with those higher bandwidths such as:
USB2.0
USB3.x
6G SATA
PCIe Gen 3
PCIe Gen 4
1G ...
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12
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Is there a small (6-pin) DIP I can use to generate multi-MHz squarewave clocks with an external crystal?
Yes, you can make a Pierce oscillator with one chip and a resistor and the two load capacitors, plus maybe a series resistor if the drive power is too great for your particular crystal.
The inverter ...
12
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How can you achieve decent clock accuracy in microcontrollers (e.g., max 1 second drift in a year)? How do digital watch manufacturers accomplish it?
The 16 MHz crystal part in your link has 30 ppm initial tolerance and 50 ppm temperature stability. It has also specified aging of 3 ppm during first year and 1 ppm per year afterwards.
To put that ...
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Computer clock technology?
It's not a "sensor", it's a generator; time is not a thing that can be directly sensed. See How does a quartz crystal work?
The crystal does not itself produce the 4GHz signal, that's done with a PLL ...
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10
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Relationship between I2C drawn energy / power consumption and data rate
The I2C data and clock lines draw power when they get pulled low. Because then power is sunk through the pull-up resistors.
While a line is pulled low it will draw 5V/4.7k\$~\Omega \approx\$ 1mA. ...
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9
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Is a 4/3 clock divider possible?
You can take your 64 MHz and filter (with an LC bandpass filter) to recover the third harmonic (192 MHz). You should also be able to use a ceramic filter with some Q reduction techniques. It's called ...
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Is a 4/3 clock divider possible?
Digital counters can divide a clock frequency by any integer. Digital logic can't directly multiply frequencies by integer values.
However, you can use a digital counter in the feedback loop around ...
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9
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Ways to observe clock signal of an STM32 MCU
Directly from the reference manual, pay attention to the last line.
Without oscilloscope you can use TIM5 to perform a comparison between two clocks.
Since TIM5 can input capture from LSI or LSE, you ...
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9
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What determines the maximum clock rate for a CPU?
The present x86 isn’t made from the ‘same process and materials’ as the 6502, any more than a modern automobile and a Model T are.
Your point is taken that they’re both based on silicon, just as cars ...
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9
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How can you achieve decent clock accuracy in microcontrollers (e.g., max 1 second drift in a year)? How do digital watch manufacturers accomplish it?
Regular digital watches don't tend to maintain time to that sort of accuracy. A few minutes a year of drift is reasonable. A lot of embedded clocks don't display the seconds, so drift is less ...
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9
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How can you achieve decent clock accuracy in microcontrollers (e.g., max 1 second drift in a year)? How do digital watch manufacturers accomplish it?
There are approximately 31 million seconds in a year, so you want better than 0.03 ppm accuracy. Some temperature-compensated crystal oscillators can manage that.
Temperature controlled oscillators ...
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8
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Does a baudrate in serial communication (USB or RS232) need to be exact?
The UARTs typically used in RS232-type serial systems work by sampling the data line somewhere mid bit according to a division of the predefined baud rate base frequency clock. As such, if the sent ...
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8
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Relationship between I2C drawn energy / power consumption and data rate
Your thinking is correct, as long as you can achieve a higher speed with the same pull up resistors.
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7
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Why do micro controllers run @ 100's MHz whilst CPUs run @ GHz?
Paul, Imagine that you wanted to increase the top speed of your car. Ignoring problems of "how much are you towing, as well?" or "Is that uphill, downhill, or on a flat straight-away?"... you might ...
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7
votes
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Correct terminology for 'clock' that doesn't oscillate?
The input B could be called "gate". Or "strobe", if the action happens on one of its edges.
It could be called "enable" or "chip select" if during it's on state it activates input A.
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7
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How does the current processor technology with low clock rates (<10 GHz) deals with mmWave (>10 GHz) technology used in 5G?
Certainly current general-purpose processors run in the low GHz clock speeds. However, purpose-designed circuits are capable of running at higher speeds. The parts of the circuit that need to handle ...
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6
votes
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Maximum SPI clock speed specified in data sheet
No, 6 MHz is guaranteed to work by the specification.
In practice you will very likely find devices which can work up to 8 or even 10 MHz. But it is not guaranteed that that will always work for all ...
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6
votes
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Capacitive load - Matching Right Crystal and Caps for oscillator circuit - DS1302 RTC - cut and trim
If a crystal has a load specification as "12.5pF", it means that the circuit will generate specified nominal frequency if the crystal is LOADED with 12.5pF, from one terminal to the other terminal. ...
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6
votes
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Does a baudrate in serial communication (USB or RS232) need to be exact?
The timings have to be accurate enough that they don't drift apart before the protocol resyncronises.
UART serial resyncronises on each byte and a byte is around 10 bits (8 bits of data plus start ...
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6
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What determines the maximum size of a cpu cache?
It's a trade-off between the higher hit rate of a large cache and the faster speed of the smaller cache RAM. Hit rate follows a law of diminishing returns as the cache gets larger.
Doubling the size ...
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