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4

Yes, that's the standard representation of a buffer. What you see are clock buffers which are present there to not degrade the rise and fall times of the clock. As typically clock nets have high fan-out, you need high drive strength to ensure that a nice square wave reaches all the registers. And yes, it introduces a delay in that path. For instance, in your ...


3

Let's assume you're referring to this type of clock termination (simulate it here): This provides 50 ohm single-ended termination for each signal as well as 100 ohm differential impedance. So all good stuff. So, why AC clock termination at all? It reduces power consumption somewhat vs. DC termination: the only power it uses is in the termination resistor ...


2

Ideally, I want to set_output_delay only for paths from internal FFs to ulpi_dir, but it only supports targets, not sources? Yes, it's possible in SDC. You can use the set_max_delay and set_min_delay instead. For e.g, if I really understood your requirement on ulpi_data: set_max_delay -from [get_registers *] -to [get_ports ulpi_data] 8.200 Where \$8.200\$ ...


2

There are TWO clocks that matter to that device, CNV (specifically the falling edge) and sclk. Sclk is gated, and runs typically at either 55 or 110MHz, but is not particularly jitter sensitive, so a clock capable FPGA pin or even a ODDR register with the inputs strapped appropriately should be just fine there. CNV is the 2MHz one that matters for this thing ...


2

A divide by 4 needs to be synchronous at these speeds sharing the master clock to minimize phase skews from the expected 90 deg shifts relative to the % of 16.67 ns per phase. But you need to specify this maximum skew to choose the right parts and configuration. Simply: 60 MHz /2 using D FF with Q,Q! With 2 clocks Driving 2 more /2 D FF’s gives 4 quadrature ...


1

Registers are normally made from D flip-flops, which transfer and hold data on the rising (or falling) clock edge. Assuming the data hold time of the flip flops is less than the propagation delay through the LUs etc., these D flip flops are all you need to prevent a race condition. The rest can all be combinatorial logic that lets the signals flow through. ...


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