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49 votes

Serbia, Kosovo power grid row delays European clocks. Why?

From the Reuter's article referenced: SARAJEVO, March 7 (Reuters) - European power grid lobby ENTSO-E urged Serbia and Kosovo to urgently resolve a dispute over their power grid, which has affected ...
Transistor's user avatar
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48 votes
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How do GPS satellites refresh their clocks

Clock errors are not corrected, they are compensated in two steps. 1. Error determination The GPS control segment uses reference receivers in well known locations to determine the actual orbital ...
Andreas's user avatar
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37 votes
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How to communicate faster than the system clock

I guess the confusion is you assume you can only send one bit per clock cycle. There are lots of ways a communication scheme can essentially encode more than one bit per symbol. A symbol is abstract ...
vicatcu's user avatar
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36 votes
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Why use DDR instead of increasing clock speed?

With SDR, there are two clock edges per bit, but only at most one edge on the data line. With high frequency communication, the analog bandwidth limits how close you can put edges together on any ...
Dave Tweed's user avatar
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33 votes
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Serbia, Kosovo power grid row delays European clocks. Why?

How a decrease in electricity production can lead to a decrease of the frequency on the grid on the long term? Isn't the frequency a parameter controlled by the power plant at the end of the day? ...
Marcus Müller's user avatar
25 votes

Why is the MCU clock out waveform sinusoidal and not square pulse

It's hard to see (or even generate) a 170 MHz ideal square wave. Use the 10:1 attenuation mode. In the 24 MHz case, you probably don't have a good ground connection on your scope probe -- you need a ...
jp314's user avatar
  • 19.7k
25 votes

Are there any microcontrollers that do not require an external clock source?

Many (most?) MCU's have an internal oscillator that can be used as the clock. Typically there will be a configuration that is held in non-volatile memory to set the clocking mode. The actual method ...
Kevin White's user avatar
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23 votes
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How do processors control their clock speed?

This is done using a device called a phase-locked loop, or PLL. Here is a block diagram of a basic PLL: simulate this circuit – Schematic created using CircuitLab The oscillator on the ...
alex.forencich's user avatar
22 votes

How can I estimate the speed of this code section for this microcontroller?

Since the code snippet you're interested in isn't big, you could disassemble your compiled code, look at all the assembly instructions and count how many cycles they need. You can find the number of ...
Swedgin's user avatar
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20 votes

Serbia, Kosovo power grid row delays European clocks. Why?

How can a decrease in electricity production lead to a decrease of the frequency on the grid on the long term? Isn't the frequency a parameter controlled by the power plant at the end of the day? You ...
Peter Green's user avatar
20 votes
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Why do some microcontrollers have numerous oscillators (and what are their functions)?

32kHz ultra low power oscillator: Used for RTCs (Real-time-clock). These can run in the background and enable time-keeping, even when the controller core is sleeping. This enables to have a running ...
jusaca's user avatar
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20 votes
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What happens if clock cycle is replaced with constant high voltage in a processor?

Your doubts arise from lack of understanding of the basics about synchronous sequential logic networks, of which modern CPUs and related basic blocks, like counters, are just particular examples. As ...
LorenzoDonati4Ukraine-OnStrike's user avatar
19 votes

Why use DDR instead of increasing clock speed?

The real problem is bandwidth. The highest frequency that a data line can generate (well, not counting slew rate) is when it's sending a 101010 data pattern, which occurs at half of the data rate. ...
alex.forencich's user avatar
19 votes

What frequency stability crystal do we need?

Too long to read all that stuff so, here's the short story From comments under the question, Trevor says this: - we think the caps are correct. We have 2x 15pf to ground. The crystal we're using is ...
Andy aka's user avatar
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18 votes
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Setup and hold time output when violated

If the flip-flop's setup time is 20 ns, it means that data has to be stable atleast 20ns before the capturing clock-edge. Similarly hold time is the amount of time, data has to remain stable after a ...
Mitu Raj's user avatar
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18 votes
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Can wireless communciation be synchronous?

Yes. Kind of, at least. As you're coming from a wired background, I'll build the analogy from there: Where UART only works because receiver and transmitter clocks are similar enough so that, for a ...
Marcus Müller's user avatar
18 votes
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1 kHz clock over long wire

So, the first problem will be that you need to drive that long cable! A 1km long piece of wire is simply a large load, and your microcontroller output will have a hard time changing the voltage on ...
Marcus Müller's user avatar
18 votes
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Does the SPI protocol specify how many clock pulses a master device should send to the slave?

The SPI master is not responsible for making sure that the slave's internal state machine gets 'enough' clock pulses. All the master is responsible for is one clock pulse per bit transferred to or ...
brhans's user avatar
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17 votes

Does the SPI protocol specify how many clock pulses a master device should send to the slave?

The answer to any question about the SPI protocol is: there is no SPI protocol! It's the simplest possible way to transfer serial data, essentially just a shift register. Have a look at a typical SPI ...
awjlogan's user avatar
  • 7,969
16 votes

gps performance for synchronization

A GPS receiver creates a local replica of something called "GPS system time", which is a virtual timebase created from all of the clocks on the satellites and ground stations. This replica is integral ...
Dave Tweed's user avatar
  • 176k
16 votes

1 kHz clock over long wire

You really need to think hard about what you really mean by "simultaneous". Over a span of 1000 meters, the concept does not extend down to the sub-ns regime. Heck, it would take a light pulse more ...
Dave Tweed's user avatar
  • 176k
16 votes

What happens if clock cycle is replaced with constant high voltage in a processor?

The clock must transition, from low to high, and repeat, in a regular pattern. It is these transitions which drive changes in the logic, not the high level. No transitions = no logic change. So ...
rdtsc's user avatar
  • 16.3k
16 votes

How can I calibrate a retail digital clock that uses a 32.768 kHz crystal?

First, refer to this post for details of (we hope) the underlying oscillator schematic. You'll probably just see the crystal and the caps, with traces going into a chip. Verify that you've found the ...
TimWescott's user avatar
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15 votes

What frequency stability crystal do we need?

If you have a suitable means of measuring the frequency, you can adjust one of the load caps with a trimcap to get closer to the ideal. However you will need some means of measuring without altering ...
Spehro 'speff' Pefhany's user avatar
14 votes
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Is there a small (6-pin) DIP I can use to generate multi-MHz squarewave clocks with an external crystal?

The LTC1799 can be programmed by a resistor and a link to produce a vast array of frequencies. Is there a small (6-pin) DIP I can use to generate multi-MHz squarewave clocks with an external ...
Andy aka's user avatar
  • 467k
14 votes
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Why does this rising edge detector using a capacitor and a resistor work?

In the video the circuit worked as if the negative pulses were nonexistent. Yes, that effect is due to the chip. Let's have a look at the SN74LS08's datasheet and look at the circuits on the chip: ...
Bimpelrekkie's user avatar
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14 votes

How can I estimate the speed of this code section for this microcontroller?

Let's do it! Say we have the code ...
yar's user avatar
  • 330
14 votes

How can I calibrate a retail digital clock that uses a 32.768 kHz crystal?

Since the clock is running fast, you could try increasing the capacitance on the crystal by using a "gimmick", which is a capacitor made by two insulated wires twisted together. Magnet wire ...
PStechPaul's user avatar
  • 7,555
13 votes
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Why is there a PLL in CPU?

There are several reasons for this. A phase locked loop, or PLL, is a circuit that is used to generate a stable frequency that has a specific mathematical relationship to some reference frequency. ...
alex.forencich's user avatar
13 votes
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Accessing odd address memory locations in 8086

Word-wide memory is addressed with a single address bus. When a word is read from an odd address, one byte is in one word, the other byte in another. You cannot address both bytes at the same time. ...
Neil_UK's user avatar
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