The part appears to be a 3.3V cystal oscillator, with an LVPECL differential output, which oscillates at 30.72MHz.
If you are making your own board based on the demo, you simply need to find an oscillator with those specs. In fact it doesn't even need to be differential or LVPECL, the CDCE62005 supports a wide variety of IO standards for its reference clock.
If CPOL—Clock idle POLarity— is low, then rising edge is used. The opposite may also be used if agreed at each end.
Correct, the term "cycle" just means the repeating active time period of both positive and negative duration in any order. ( ignore idle time )
It is because the data strobe encoding scheme improves skew tolerance to just under 1 clock period vs. just under half a clock period for a traditional data + clock encoding scheme.
With data + clock, if the clock transition is half a period earlier or later, it is no longer clear which data bit belongs to which clock cycle.
With data strobe encoding, since ...