8
votes
Why is my crystal oscillator (4 pin DIP 4 MHz unbranded from ebay) producing unusable clock signal waves?
The oscilliscope you linked to has a 200 KHz bandwith - it will not show anything near the correct waveform and voltages of a 4 MHz signal.
- 60.2k
7
votes
Accepted
10MHz reference vs 1 PPS vs GPSDO
A GPSDO is a way of providing a 10MHz reference. A GPSDO can be an external device, but some SDR devices are also able to "host" a GPSDO so that you don't need an external unit in its own ...
- 7,948
7
votes
Accepted
What would cause a router CPU to run 44x slower?
I can't tell you how to fix the problem, but I think I can explain what is going on.
All versions of the TP-Link Archer C9 use a 1GHz processor. You say that there's a 25MHz crystal on it and that it ...
- 73.1k
6
votes
Accepted
Why I am getting one clock cycle delay in Verilog case statement?
At the positive edge of clk you change from WAIT state to SERVE state. You don't change the ...
- 68.7k
6
votes
Using a function generator as a clock source to drive several ICs (CD4000 CMOS series & 74 TTL)
I tried to use it but I have a hard time getting the circuit to work, firstly when adjusting the amplitude to be 5V peak (+5-5) square wave
It should be 0V..5V, not -5V..+5V!
the ICs don’t seem to ...
6
votes
Accepted
Detect presence of 12MHz squarewave without oscilloscope
With a multimeter measuring voltage:
Assuming the esp32 signal source has 50%/50% duty cycle, measure the DC voltage at the output pin...it should be about half of esp32's Vdd. Otherwise, you'll ...
- 27k
5
votes
Clock Signal over long distance
An electric signal moves about 5ns per meter. If you have about 30cm between each device, that's about 5 meters. It takes a clock edge about 25ns to travel from MCU to last mic, and it takes up to ...
- 164k
5
votes
Accepted
Different ways of fanning out low jitter clock signal
Answering your questions in order:
Whether or not you can fan out directly without a buffer will depend in signalling standard used for the clock, and the number of devices you are connecting to.
...
- 68.7k
5
votes
Forwarding a clock and display it on oscilloscope
Set the probe on x10, make sure there is no BW (Bandwidth) limit set in the oscilloscope on the active channel and carefully adjust the probe compensation (an adjustment screw in the BNC end of the ...
4
votes
Why I am getting one clock cycle delay in Verilog case statement?
The other answer directly answers your question about the relative timing of your output signals, and it also provides an astute observation of a probable bug in your code (...
- 8,771
4
votes
Accepted
How to get a clean clock signal from FPGA to DACs?
As far as I know, FPGA are never a good choice to source a clock from, if you care about jitter. And with DACs, you almost certainly do care.
Use a PLL based clock buffer, that provides a synchronous, ...
- 22.8k
4
votes
Clock Signal over long distance
Instead of daisy-chaining the signal you could connect it in a star fashion, a cable from each microphone to the clock source with each cable being the same length so the propagation delay is the same ...
- 26k
4
votes
Accepted
On a method of clock gating with a latch
The latch-based clock gate logic helps to prevent glitches on the clock output signal from the clock gate, assuming appropriate timing constraints are applied when synthesizing/implementing the design....
- 8,771
4
votes
Accepted
What does an AND gate inside a box mean?
Figure 67. Bus clock enable logic shows a little more detail. The sys_ck input to the SCGU is shown as a 2-input AND gate. One ...
- 8,771
4
votes
What does an AND gate inside a box mean?
The and symbol is a gate for enabling the clock for cpu core or peripherals. On input will be controlled by a register. This looks like an STM32 bus-structure so likely the reset and clock controller ...
- 17k
4
votes
Accepted
24MHz Clock Signal Distortion
It looks exactly as expected. There is a lot of paths for echo to be reflected back and forth through the length of each column and its lateral feed, and these echoes will propagate past the driver ...
3
votes
Clock Signal over long distance
We call these things circuits because current flows in circles. One of the most important considerations for dynamic signal integrity is that every signal wire should have a return wire close to it. ...
- 4,907
3
votes
Detect presence of 12MHz squarewave without oscilloscope
I want to detect that the esp32 is outputting the signal out of the intended pin.
The following circuit will light up both LEDs if its input has both high and low signals. It can be implemented using ...
- 26.1k
3
votes
Detect presence of 12MHz squarewave without oscilloscope
Your ESP32 has a "pulse counter" peripheral, which you can program to raise an interrupt every 216 rising input edges. Nice! Route your output pin back to another pin on your ESP32, and ...
- 98.3k
3
votes
Internal system timer oscillations on modern computers - how big can it be?
Commercial-grade 100 ppm oscillators — the type used in most computers — can deviate from each other by about 1 second in 10,000. 60 ms in 10 minutes and 2.88 seconds in 8 hours is consistent with ...
- 176k
3
votes
Internal system timer oscillations on modern computers - how big can it be?
A 25ppm (parts per million) difference in clock frequency means that after 1 hour (3600 seconds) the difference would be 90ms.
25ppm or 50ppm difference between two crystal oscillators would be of the ...
2
votes
What's the difference between a latch and a flip flop? I found multiple answers
This is intended as an answer to the terminology question.
Why do so many textbooks and online resources call the upper circuit a Flip Flop, when it basically works as a latch?
Because different ...
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2
votes
Accepted
What's the difference between a latch and a flip flop? I found multiple answers
Unfortunately, there is a great deal of confusing usage out there. Many people, myself included would describe an edge triggered memory element, and only an edge triggered memory element as a flip-...
- 26.1k
2
votes
Underclock the microprocessor
If a microprocessor specifies a minimum clock frequency, it means that it uses dynamic logic internally. If you underclock it, you may experience failures because internal nodes don't get refreshed ...
- 176k
2
votes
Pulldown resistor on CLK input of 74HC109
I'm guessing Mr. Donald knew that the 741's output was unable to get close enough to ground to register a "low" at the 74109 input, and had to resort to brute force, by pulling it down in ...
- 42.2k
2
votes
Accepted
What is the fastest achievable output speed for an FPGA?
The other answer has addressed the xor_clk part of the question.
As for this part of the question:
To sum up the question, I would like to know what is the maximum ...
- 6,153
2
votes
What guarantees are there on when GPIO states are read and written?
It depends on the MCU.
For example, on an AVR, if you set an IO pin output state, you need to delay in software at least one clock cycle with a NOP before reading the pin status, to read back the ...
- 164k
2
votes
Accepted
How do I call a module repeatedly in Verilog, in sync with a clock?
First, apart from your basic question about calling a module repeatedly in Verilog, there are alot of mistakes in your code:
address is not being driven by any ...
- 402
2
votes
Accepted
Adding on and off state in a 555 timer clock circuit
Basically i want the clock turn on when a constant high input is in and turns off when the it is low (kinda like a switch)..
Use \RST pin (pin #4).
It's an active-low input so when it's tied to ...
- 38.1k
2
votes
Detect presence of 12MHz squarewave without oscilloscope
You can achieve "envelope detection" with a single diode, slightly better with two, plus a small capacitor and a resistor.
The diode needs to work at the frequency of interest - "MHz&...
- 151k
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