New answers tagged clock
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Underclock the microprocessor
A generic answer for generic question; it depends on the MCU. If it defines a minimum operating frequency, it is there for some reason.
It might not affect anything if it uses static logic. But in ...
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Underclock the microprocessor
If a microprocessor specifies a minimum clock frequency, it means that it uses dynamic logic internally. If you underclock it, you may experience failures because internal nodes don't get refreshed ...
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Pulldown resistor on CLK input of 74HC109
I'm guessing Mr. Donald knew that the 741's output was unable to get close enough to ground to register a "low" at the 74109 input, and had to resort to brute force, by pulling it down in ...
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What is the best way to use 0 ohm resistors for a large number of signals?
It may not be appropriate in your particular case, but you can get x4 (and other multiples, but x4 is more common) zero-ohm networks. Image from lcsc shows a part measuring 1 x 2mm overall.
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What is the best way to use 0 ohm resistors for a large number of signals?
Those of us old enough to remember configuring motherboards know that if there are a lot of these to do, there are really two options: switches (available in SPST and SPDT, at the very least) and 0.1&...
- 29.6k
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STM32G431 CMSIS clock setup failed
The code is intended for another MCU model. It may not work on another MCU model if the RCC peripheral is different.
You are also reading the register default value and ORing your values on top of it. ...
- 137k
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Slave SPI not firing interrupt
I solved it, my GPIO alternating function configuration wasn't working properly... i forgot to subtract 8 on the high register which explains why SPI1 was working and the other two SPI2/SPI3 were not.
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Why I am getting one clock cycle delay in Verilog case statement?
The other answer directly answers your question about the relative timing of your output signals, and it also provides an astute observation of a probable bug in your code (...
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Accepted
Why I am getting one clock cycle delay in Verilog case statement?
At the positive edge of clk you change from WAIT state to SERVE state. You don't change the ...
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How to generate a clock signal using an op-amp
When operated on a single supply, with its negative rail tied to GND, a 741 output stage cannot produce a TTL low signal level. IOW, the output cannot swing all the way down to +0.8 V (or less) above ...
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STM32F407 PLL config not producing 1ms SysTick
uint32_t pllp = 2;
RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLP_MASK;
RCC->PLLCFGR |= (pllp << RCC_PLLCFGR_PLLP_POS);
RCC_PLLCFGR.PLLP does not contain ...
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How to get a clean clock signal from FPGA to DACs?
As far as I know, FPGA are never a good choice to source a clock from, if you care about jitter. And with DACs, you almost certainly do care.
Use a PLL based clock buffer, that provides a synchronous, ...
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How to get a clean clock signal from FPGA to DACs?
If the spec for the DACs calls for an LVPECL clock source, you can easily generate a LVDS/LVCMOS clock output from an FPGA, and then utilize a clock buffer to perform the interface translation for you....
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