# Tag Info

3

I have assumed that you just want a high pulse out during the high phase of the clock every 64th clock pulse. 4024 is a negative edge triggered 7 stage binary counter. 4068 is an 8 input Nand gate. 4013 is a Dual D-Type flip flop. Output of nand gate is usually high holding D type flipflop in reset. On a certain falling edge of the clock, the counter will ...

2

Ripple counter, and a one-shot trigger type thing if you want to shorten the extracted pulse.

0

Everyone else has the facts (low power applications etc) but the motivation is reduced chip count. SoC (system on chip) is used in commodity devices for which the dominant constraints are size battery life low part count Such devices need often need many or all of the capabilities mentioned in other answer. Getting all of these features - especially ...

18

32kHz ultra low power oscillator: Used for RTCs (Real-time-clock). These can run in the background and enable time-keeping, even when the controller core is sleeping. This enables to have a running clock without the high power consumption of the controller core. The 32kHz oscillators are pretty precise and typically have an error of less than a minute per ...

6

Here is the clock configuration in block-diagram form from ST's configuration tool (STM32F103). As you can see, there are internal oscillators and two oscillators that use external frequency-determining components (crystals or resonators typically). I have this configured to use an external 8MHz crystal and a 32.768 kHz watch crystal. I could have used the ...

3

The ATSAM family controllers typically have one really slow 32kHz oscillator used for low power applications, either with internal RC oscillator or external quartz crystal. And one high speed internal RC oscillator for "fast as it goes". In addition you can tweak around with PLL's, clock dividers and so on, and of course also provide external ...

10

What these are for: 32kHz low power: "digital watch" crystal. Use this when you want to power down the main oscillator but not lose track of what time it is so you can wake up periodically. 32kHz RC: cheaper (no crystal), but less accurate. When you want a digital watch that doesn't tell the correct time. external fast crystal: for things like ...

8

They are not strictly necessary but the vendor is attempting to cover as many use-cases with one part as they can. Some applications may want to use the internal oscillator, others may need a precise clock source, others may want low power consumption. Generally you will use only one in a specific design although in some cases the clock mode is changed ...

1

I know it's a little late, but I have been pondering the same thing, and searching the internet for ideas. Although what I was really looking for was validation of my own idea. I have a cheap alarm clock that I bought for exactly this purpose. It operates from a 1.5V AA cell, and has a Lavet mechanism internally. My idea is to set the alarm to 12:00 and ...

0

I plugged the LED in the wrong way around to test the output on Q8. Stupid error. Thanks.

0

Just providing an update to this question. As per everyone's advice, I had modified my VHDL to clock the design and the problem is solved. This allowed the synthesiser to use clock capable pins for the clock and the other pins for the set and enable input. It has however caused me more issues throughout my complete design as I have this same issue in other ...

3

For an ultra-low-power design, only low-frequency crystals are usable, because with the frequency increase the current consumption increases significantly. The article The Strengths of 32.768 kHz Oscillators is undoubtedly a commercial, but I venture to mention it because the article excels, first of all, the technological advantages of generic tuning fork ...

1

what I don't understand is that why t_skew will be "harmful" when talking about T_hold? Hold violation happens when the data launched by FF1 reaches FF2 "too earlier" than it is supposed to be. Suppose a data was launched by FF1 on the clock edge at a time $t$. After a clock skew of say $\Delta t$, the same clock edge reached FF2 at \...

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