3
votes
Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in saturation?
MOSFET drain current is:
$$ I_D = k(V_{GS} - V_{TH})^2 (1+\lambda V_{DS}) $$
for \$V_{GS} > V_{TH}\$, where \$\lambda\$ is the fractional change in current due to channel length modulation, and:
$$ ...
- 42.2k
2
votes
Drain current spiked during switching in CMOS Inverter
here I see that there is a spike in the negative direction as well
What you are observing is a current surge due to charging and discharging the drain source capacitances of the MOSFETs inside your ...
- 467k
2
votes
Accepted
Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in saturation?
A simple argument can be constructed without knowing the output (drain) impedance at all, whether triode, saturation or channel-length-modulated:
Since the drain current of each N/P-MOS is a one-to-...
- 43.3k
1
vote
How to eliminate the burrs in the results of HSPICE simulation of CMOS composed xor gate
An XOR gate has what is called a functional hazard. If you change two inputs simultaneously, or near simultaneously, the gate may glitch, as in your simulation. This type of hazard cannot be fixed by ...
- 26.1k
1
vote
How to eliminate the burrs in the results of HSPICE simulation of CMOS composed xor gate
Those glitches are possibly capacitively coupled feed-through from the inputs directly to the output. The transistors' parasitic capacitances \$C_{GD}\$ and \$C_{DS}\$ are at fault, and are ...
- 42.2k
1
vote
Why does current mirror need a diode connected configuration?
Short answer
Connecting a transistor's gate to its drain introduces negative feedback, reversing its operation. Instead of converting voltage to current, it now converts current to voltage. By ...
- 18.2k
Only top scored, non community-wiki answers of a minimum length are eligible