# Tag Info

41

It is generally a good idea to include a gate resistor to avoid ringing. Ringing (parasitic oscillation) is caused by the gate capacitance in series with the connecting wire's inductance and can cause the transistor to dissipate excessive power because it doesn't turn on quickly enough and hence the current through drain/source in combination with the ...

34

You're mixing up implementation technology with colloquial terms for functionality. CMOS - Complementary Metal Oxide Semiconductor - is a method of making logic and related circuitry using both N-Channel and P-Channel field effect transistors. One of its defining characteristics is extremely low static power consumption - power is almost only used when ...

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In a word: Efficiency. You can use a PMOS transistor to drive a logic output high (e.g. VDD) when the input is low (e.g. GND). However, you can't use that same PMOS transistor to drive a logic output low when the input is high. When you drive the input high in your PMOS inverter, it turns off, leaving the output effectively high-impedance, which is not ...

27

When I have a camera, that can take still images at 10fps with a mechanical shutter, why doesn't it mean the sensor can take images at 10fps electronically without producing rolling shutter? In order to understand why, we have to take a look at a typical 3T(ransistor) pixel: This 3T pixel can be used with rolling shutters, but not with (electronic) global ...

27

Paragraph 2 of the description says: FAN3100 drivers incorporate MillerDriveTM architecture for the final output stage. This bipolar-MOSFET combination provides high peak current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing rail-to-rail voltage swing and reverse current capability. ...

24

What is 180 degrees phase shift? When the signal is a sine wave, a 180 degrees phase shift delays the signal for half the period of that sine wave, the sine wave then looks inverted: Can an inverter do this? No, because it has signal gain, the output would be a square wave, not a sine. When the signal is a square wave with a 50% duty cycle, then something ...

21

if X or Y on both PMOS transistors is 0 , then both transistors will be open and the output will be 0 because there will be no flow of the current. The output will not be '0', it will be floating. That will leave any connected devices with a floating input and very susceptible to noise. The connected devices also have input capacitance and these need to be ...

20

That's not a protection device, if you intend "protection" as something that prevents the chip to die, but it serves as a so-called bypass capacitor. It acts as a reservoir of energy whenever the chip draws pulses of current when switching occurs. If the power rails were truly ideal connections, with no resistance nor inductance, bypass caps wouldn't be ...

20

Yes, CMOS circuits can get hot when there are floating inputs. You should always connect unused CMOS input pins to a defined voltage, usually GND or Vdd, unless the datasheet tells you otherwise (see also the end of this answer and Michael's answer). If a pin could be configured as either input or output and you are not sure which it will be, then you could ...

18

There are two parts to this: First, rolling shutter can still occur with (some, see note) mechanical shutters. However, this is only at short exposure times. The shutter is built out of two curtains. Before the exposure, curtain 1 is in front of the sensor. When the exposure starts, curtain 1 moves down (or up or whatever) and starts exposing the sensor. At ...

18

You make the common, and mistaken, assumption that a node that is not actively driven (has zero current flowing) must be at a low voltage. That is not true. The output of the gate must be pulled down or it can not operate reliably. Without a pull down of some kind the output voltage is indeterminate. You could use a resistor pulldown but that will waste a ...

17

You do not strictly need a base resistor. Not only do MOSFETs not have bases (they have gates), but the gate is (very) high impedance. Except when the MOSFET is changing states, the gate current is essentially zero. Sometimes, a gate resistor is prudent to reduce ringing, especially if the trace driving the gate is long, or if you are concerned with ...

16

A custom chip for 10k units is unlikely to be cheap, as the masks will almost certainly cost more than $1k, which means your chip cannot possibly be made for$0.10. The reason the one you've found costs $0.10 is because they sell in a much greater volume (100k-millions), so the cost of masks and setup for a production run is spread over many more units. ... 16 The dashed line means that the diode is actually distributed across the resistor structure. The resistor is made using a doped region in the silicon, and there is an inherent PN junction between this doped region and the underlying silicon that contains it. So there is really just one diode, not two, but it is neither before nor after the resistor...it is ... 14 Fundamentally, a buffer is an amplifier. It takes a small signal (lightly loading the source of the signal) and provides a copy of that signal that can drive a heavy (e.g., capacitive) load. They are used in places where connecting the heavy load directly to the source would adversely affect the signal. Such effects arise because the signal source has a ... 14 I would say its the width of the exposed part of the sensor: you can have a slit that is 1mm move across the sensors, or 10mm, etc. Probably useful to write as a ration, 10% of the sensor width/height. Added: RM What Sandos said above. Expanding on that. A rolling shutter (Wikipedia) is a camera (or image) sensor technique that produces exposure times ... 14 Back when the PC was first invented, most of the logic on it was power-hungry NMOS and TTL chips. CMOS was very new and the only circuits in the PC that used it were associated with things that needed to run on battery when the power was off, such as configuration RAM and the real-time clock. Nowadays, nearly all of the logic is CMOS, including the power-... 14 If a very large MOSFET (i.e. with a very wide channel) was implemented as a single physical device, like the one you saw in class, then the gate electrode would be very long and thin. This would cause a significant RC delay down the gate and so the MOSFET would turn on and off very slowly. Furthermore, it would be difficult to put such a device in a package ... 14 This is a case of interface between logic families (from LS-TTL -to- CMOS). Although both are powered from +5v supply, logic levels differ: Logic low output for the 74LS93 is compatible with logic low input for CMOS 4002. No problem here. Logic high output of 74LS93 is marginal compared to logic high input for CMOS 4002. This is a matter of noise immunity: ... 13 A Schmitt trigger inverter is a bad idea for the first inverter which is driving the crystal directly. It may not even oscillate at all as shown, or oscillate at some undesired frequency. Note resistor R1. That is supposed to bias the inverter as a linear amplifier close to the middle of its output range. The little bit of noise generated by the inverter ... 11 Here is a (slightly dated) paper that discusses the differences: http://www.ece.neu.edu/faculty/ybk/publication/ASSESSING_MERDRAM_ELSEVIER.pdf Basically, it boils down to a few important differences. Leakage current. The pass transistors for the DRAM cells must be extremely low leakage, otherwise the leakage current will affect the bit stored in the ... 11 Depends on the environment. Maybe in your circuit above and in an FPGA they are the same but in an ASIC library you find differences between the various inputs. 11 The CMOS and BJT output stages are combined to from one stage, the manufacturer calls this a "MillerDrive(tm)". Why they do this is explained in the datasheet: My guess is that they want to achieve a certain (output drive) performance that cannot be achieved by only using CMOS transistors or only using the NPNs with the manufacturing process that they're ... 10 There will be a very small difference in that circuit because of the differences in VGS in the N stack while the circuit is sinking current during switching. M1 will be marginally slower than M2 under some conditions. There are however likely to be other factors, say in how the circuit is laid out, that will have an equally large effect. Define perfect. ... 9 This is not a direct answer, but nonetheless relevant information. While it is true that old TTL would interpret floating inputs as high, this was never something to be relied on in a real design. The inputs floated only a little above the threshold, so the noise margin was low. Because they weren't actively driven, the impedance was high. Between these ... 9 I think you are confusing two usages of the "CMOS" acronym. There are chips built entirely of the complementary MOS transistor technology. In fact almost all chips these days are built this way including much of the digital control circuitry on a Flash chip. The other usage of CMOS has persisted in the PC industry since the earliest days to refer to the ... 9 Notice how the top NPN can only make the output reach VDD-0.7 V, I assume it is the job of the mosfet to take care of the last 0.7 V. It looks as if the BJT's are doing most of the grunt work and the mosfets are taking care of making the output reach VDD and a strong GND. I could be wrong though. 9 First, I "markup" your circuit drawing with logical element regions (two inverters, three NANDs): Then redraw it as digital circuits are drawn: simulate this circuit – Schematic created using CircuitLab and calculate the output: NANDA outputs $\overline{A · \overline{B}}$ NANDB outputs $\overline{\overline{A} · B}$ NAND_OUT outputs \$\...

8

How do they work? They have integrated charge pumps to create internal supply voltages that are greater than ±25 V. Is it simple to build a circuit like this out of discrete parts? Possible? Yes. Simple? Not particularly.

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Like others have already said (I'll just be a little more elaborate), unused CMOS input pins must never be unconnected, because they tend to float towards the dangerous region which is in the middle between VDD and GND. The input pin invariably is connected to another complementary MOS pair's gates, and the process parameters are often optimized for ...

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