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21

if X or Y on both PMOS transistors is 0 , then both transistors will be open and the output will be 0 because there will be no flow of the current. The output will not be '0', it will be floating. That will leave any connected devices with a floating input and very susceptible to noise. The connected devices also have input capacitance and these need to be ...


18

You make the common, and mistaken, assumption that a node that is not actively driven (has zero current flowing) must be at a low voltage. That is not true. The output of the gate must be pulled down or it can not operate reliably. Without a pull down of some kind the output voltage is indeterminate. You could use a resistor pulldown but that will waste a ...


9

First, I "markup" your circuit drawing with logical element regions (two inverters, three NANDs): Then redraw it as digital circuits are drawn: simulate this circuit – Schematic created using CircuitLab and calculate the output: NANDA outputs \$\overline{A · \overline{B}}\$ NANDB outputs \$\overline{\overline{A} · B}\$ NAND_OUT outputs \$\...


8

That looks like a tristate-capable output buffer, as used on the output pins of various microcontrollers. It can be set to output a value, disabled (floating/tristate), or to have weak active pullup.


6

Doesn't the circuit work without them as well? No it does not, the PMOS + NMOS circuit is called a passgate or transmission gate. So this circuit has two passgates, C0 and C1. In order to be able to conduct a high signal, the PMOS is needed (then the NMOS does nothing). In order to conduct a low signal, the NMOS is needed (and the PMOS does nothing). ...


6

Was it because the transistors in those early microprocessors were microscopic instead of nanoscale? Mostly yes. Larger geometries and higher voltages are less susceptible. Early processors ran on 5V, now processor cores are in the 1V range. You also must consider the consequence of an SEU. Most people were not doing serious work with the processors that you ...


4

Consider this better diagram of the actual MOSFETs inside a transmission gate: - Look closely and you'll see that the bulk connections for each MOSFET are not tied to their respective source nodes but to opposing power rails. This ensures that when a particular MOSFET is deactivated, the body diode that might normally conduct (and would ruin the "OFF" ...


4

You do have floating inputs. You simply replaced the VCC wires to DIP switches with resistors. So again, when DIP switch is closed, the chip input is connected to VCC via resistor, which is fine. When DIP switch is open, the chip input is connectes to nowhere and floats.


4

For small signal, I would recommend thinking of this simply as two parallel (but complementary) transconductors (or CS amplifiers if you want to look at it like that). If I redraw it, perhaps it makes it more obvious: In a small signal sense, a NMOS CS amplifier is no different to a PMOS CS amplifier, so a parallel connection will simply give you a combined ...


4

The short loop delay pulse duration is insufficient for your 4xxx series CMOS which is much slower than 4040 . Even though 74HCxx logic family is much faster, you still need to stretch the pulse by adding feedback delay.


4

I don't understand why we use contacts to connect poly... but we can't connect it [poly] to the active area. First of all, metal1-poly and metal1-active are perfectly fine as you mention. It's poly-active that doesn't make sense. The reason is that poly happens to affect the active area when fabricating self-aligned gates. Recall that the active area is ...


3

Q1 is a p-channel MOSFET (aka "PMOS"). It turns "on" when the potential difference between its gate and source (\$V_{gs}\$) is negative. But where is its source connected? It's not connected to ground (in fact, none of its terminals are connected to ground). It's connected to Vdd. So what turns Q1 on is having the input voltage (its gate voltage) ...


3

There is no right or wrong way. For a given type of FET there are many different symbols. When you make a book, you have to select a symbol and stick to it, sometimes it is a personal preference, or something the book author has learnt during his studies. The symbols used by Boylestad seem to be more commonly used.


3

Correct. Add a pulldown resistor to discharge the parasitic gate-source capacitance of the input MOSFETs of the flip-flop. It can't drain backwards through the diodes when the anode of D1 and D2 go LO so once charged HI it stays HI.


3

The green FETS, 4 of them, allow rail_to_rail operation of the four nodes, while (this is important) preventing high voltage stresses on the rail_referenced FETs.


3

You can use an op-amp to provide feedback control to mostly eliminate the load dependence: simulate this circuit – Schematic created using CircuitLab In comments you said the reason you have not considered using an op-amp is "I have area and power constraints". But your proposed solution is to use a second MOSFET. Very likely you can find an ...


3

Intuitive explanation Basic ideas. Electronic circuits, like any human creation, implement basic ideas... concepts... and to truly understand circuits, basic ideas behind them must be seen. These ideas are simple, clear and intuitive; they are a result of the human imagination in the mind of inventors. Their specific implementations require a lot of ...


3

Decreasing the voltage decreases the maximum frequency that can be used such that the operation of the digital system is as desired. This is because the equivalent resistance, \$R_{eq}\$, of the MOS transistor increases if \$V_{dd} < V_T\$. \$V_{dd}\$ is the supply voltage and \$V_{T}\$ is the threshold voltage. As the equivalent resistance increases the ...


3

That's a pretty bad explanation in the book. MOSFETs have a threshold voltage. This is the minimum voltage difference between the gate terminal and the source terminal that will allow the transistor to conduct significant current. For an NMOS transistor, the threshold voltage is a positive voltage, and the "source" terminal is defined to be which ...


2

Yes a TVS Diode, unidirectional, can protect your MCU if the fuse blows fast enough before the TVS diode gets burned itself. So you must use a fast blowing fuse with the smallest amperage possible. (Your symbol shows a bidirectional and it's not necessary.) You didn't explain what type of signal will come from the MCU. Is it on/off, low frequency or high ...


2

Zeners, particularly low voltage ones, leak far more than the CMOS input (1uA is a very loose specification at high temperature). For example, 100uA at 1V for a 2.2V zener. So I suggest you lose the Zeners and use a different kind of clamp. For example, a diode clamp to a 2.5V shunt reference for each input. You only need one 2.5V shunt reference, but each ...


2

While you can just leave the unused output open as you have shown, you should also shutdown that channel by tying the SD2 input high. As seen in the datasheet table, this won't change Is, the pin 2 power drain. But it will lower Idd, the pin 11 power drain, since the dynamic part of that is specified "per channel"--and will dominate at high ...


2

simulate this circuit – Schematic created using CircuitLab Try simulating the above schematic. The R1/R2 voltage divider will reduce the signal that is either 5V or 9V to a lower voltage. 9V –> 3.5V @ VA 5V –> 1.9V @ VA So when it is 9V the 9V will bias the R1/R2 so that VA is higher than Q1 emitter and Q1 will be off. When it is 5V it will allow ...


2

normally dry etching is more common due to its directional (anisotropic) process. Anisotropic process has the minimum bias (almost 0) and leakage of transistor that fabricate by this characteristic is less than a transistor with wet etching that has a large bias.


2

When using an NMOS for pull-up, for the NMOS to be fully on, you would need a gate voltage that is higher than the supply voltage, see the left schematic: simulate this circuit – Schematic created using CircuitLab Without that higher voltage, shown in the right schematic, you cannot switch the NMOS on fully, the output voltage will be less than the ...


2

Buffer output must be enabled to see anything on the output. Ground the OE pin to enable it.


2

"Big" values for those components is intended to indicate that they only affect the DC characteristics of the circuit, and are irrelevant with respect to the signal. The big capacitor decouples the DC from the preceding circuit, and the big resistor applies negative feedback for the Q point, such that the transistor whose gate it is connected to ...


2

Static CMOS designs rely on complementary behavior of NMOS and PMOS devices. So take a look at what will turn the top part "on" - A is 0 or B is 0. What does this do? It makes the output high. Since the bottom part is in series, for a path to exist to ground, A and B must be 1 (NMOS - so "active high"). What does this do? It makes the ...


2

The arrow shows the current flowing through the channel of the nMOS element of the left gate, as that transistor turns on due to a rising Vin voltage, as the Cw distributed capacitance discharges. On the right, Cw is connected to the gate of the MOSFETs, which are insulated from the channels. There is no path for current to flow to ground through the right, ...


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