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1

MOSFETs turn on and off based on the voltage DIFFERENCE between the gate and source terminal. That's all they care about. They don't care about GND or anything else. When you say: (won't it only turn on when Vin is negative) ? You are saying when Vin is negative relative to GND. Just saying "the voltage at the gate" implies you referencing to GND. But ...


3

Q1 is a p-channel MOSFET (aka "PMOS"). It turns "on" when the potential difference between its gate and source (\$V_{gs}\$) is negative. But where is its source connected? It's not connected to ground (in fact, none of its terminals are connected to ground). It's connected to Vdd. So what turns Q1 on is having the input voltage (its gate voltage) ...


1

Q1 is a PMOS, so the "turn-on" condition is Vgs (gate-source voltage) < -Vt. Vgs here is defined as vin - Vdd. So when Vin = 0, the gate-source voltage is sufficiently negative for turn-on.


0

Part 1: The "tiny random spikes on the output signal" in the red oscilloscope trace are noise from the circuit (at test point "IN") that provides the input to the FET gates in your CMOS inverter. IN is equal to Vin (principal square wave) plus Vnoise (100 kHz sine wave). The square wave varies from 0V to 5V. The 1.5V peak noise is added to this, producing a ...


0

You have a PFET at the output instead of a PNP, so you should not worry about any current going into the PFET's gate. Sure, there is a current (i.e gate charge) that flows into it when turning it on or off and that mainly determines how fast you can operate the PFET. Now, in the configuration you show, the PFET will always be ON. That is the case because at ...


1

They can be different. Usually in logic circuits, the optimal size (for sped and power consumption) is to have all devices at minimum allowable channel length -- the widths may differ. For analog circuits, different lengths are appropriate for different functions. This cannot be summarized in a single answer, but for example differential pairs of opamps ...


0

PSRR depends on the high-frequency gain of the regulator feedback loop. If the power-dissipation device has lots of capacitance to charge and discharge, them the regulator loop needs HIGH operating current. However, the LDO also needs suitable awareness of the risks of sloppy attention to IC LAYOUT. Diagnosing an LDO with poor PSRR even at 60Hz, I ...


0

For those who have not run across them, stick diagrams are a crude form of IC layout that emphasizes the order and placement of transistor gates, sources, drains, and so on. The stick diagrams define individual "cells", such as the 2-input and 3-input NAND gates. The method of connecting the cells depends on the the target implementation technology. If you ...


0

Either n or p may be used as load or driver depending on spec as the devices are mostly complementary. IC technology builds both nmos and pmos devices in the same substrate however and as a result, the devices will have different behaviour-- n and p thresholds and mobility will be different so that one device may be 'better' than the other, depending on ...


0

In general analog CMOS IC design (general normal speed opamps, comparators, circuit where noise is not a problem, so on) it does not really matter, if only you do not have such design that needs to be extremely noise aware, RF or of other reasons. In reality, for example during opamp design (where such CS stages are used), you get other requirements that you ...


0

Based on the transistor sizes i presume this is IC level stuff. If so start with a voltage source / resistor as a reference current. Then use 2 (or more) transistors as a current mirror. Use that mirrored current to charge your sampling capacitor with a fixed current and your get a linear slope. Your input voltage would then be operating a transistor that ...


0

As mentioned by @analogsystemsrf, the capacitance varies, so a .TRAN analysis will be a bit more involved, but since this is SPICE world you can measure it easily in .AC by adding a current source at the input with ac 1 as value and the impedance will be Vin/Iin. Since Iin is unity, you can read the value of the impedance in Volts as Vin: I didn't use your ...


0

The input capacitance will vary, perhaps greatly, as the input voltage slews between the rails. Similarly the output resistance, though not greatly (maybe 2:1), as the input voltage slews between the rails. By measuring the input (transient) current during slewing, you can compute the Cin. Note the heavy Cload will slow the output and thus reduce the ...


-1

From:Introduction to Microfabrication 2nd Edition by Sami Franssila Plasma etching is a technology that enables narrow linewidths and high aspect ratios. It has completely replaced wet etching for feature patterning in modern ICs and it is mandatory in polysilicon surface micromechanics. It has also been applied to structures and applications that ...


2

normally dry etching is more common due to its directional (anisotropic) process. Anisotropic process has the minimum bias (almost 0) and leakage of transistor that fabricate by this characteristic is less than a transistor with wet etching that has a large bias.


4

Consider this better diagram of the actual MOSFETs inside a transmission gate: - Look closely and you'll see that the bulk connections for each MOSFET are not tied to their respective source nodes but to opposing power rails. This ensures that when a particular MOSFET is deactivated, the body diode that might normally conduct (and would ruin the "OFF" ...


6

Doesn't the circuit work without them as well? No it does not, the PMOS + NMOS circuit is called a passgate or transmission gate. So this circuit has two passgates, C0 and C1. In order to be able to conduct a high signal, the PMOS is needed (then the NMOS does nothing). In order to conduct a low signal, the NMOS is needed (and the PMOS does nothing). ...


0

It looks like M1 and M4 have the D/S reversed: M4 can't have its drain grounded while the source is above ground, and M1 needs to propagate the signal from input to output, and that will be from drain to source. I'm no expert in CMOS, but from what I remember, 0.5u/0.25u signifies L/W, but I have met W/L, too. Since I can't find in the linked document what ...


2

simulate this circuit – Schematic created using CircuitLab Try simulating the above schematic. The R1/R2 voltage divider will reduce the signal that is either 5V or 9V to a lower voltage. 9V –> 3.5V @ VA 5V –> 1.9V @ VA So when it is 9V the 9V will bias the R1/R2 so that VA is higher than Q1 emitter and Q1 will be off. When it is 5V it will allow ...


1

One possible way to do this is to use a voltage divider to provide a 1.5V reference point ( about half of 3.3V). Then use a comparator to compare input to this reference point. Since 9V/5V is too large, we can use another voltage divider to provide a suitable voltage. Take the midpoint of the 9V and 5V, ie 7V as the point you’d like to distinguish 9V and 5V ...


5

To really check on what really is the correct symbol for what, you should refer to particular standards. Below is what the IEEE 315-1975 standard (which can easily be accessible online if you look on Google) tells us, for an example... (the IEC label nearby also indicates that it's ubiquitous to IEC standards as well) You can claim that this is old ...


3

There is no right or wrong way. For a given type of FET there are many different symbols. When you make a book, you have to select a symbol and stick to it, sometimes it is a personal preference, or something the book author has learnt during his studies. The symbols used by Boylestad seem to be more commonly used.


1

Save yourself all the trouble and go with a chip designed to do the job like the LTC6813: - The zener idea is flawed and realistically, you need to measure each one to ensure they are balanced so, just go for the chip solution (or a variant of it).


2

Zeners, particularly low voltage ones, leak far more than the CMOS input (1uA is a very loose specification at high temperature). For example, 100uA at 1V for a 2.2V zener. So I suggest you lose the Zeners and use a different kind of clamp. For example, a diode clamp to a 2.5V shunt reference for each input. You only need one 2.5V shunt reference, but each ...


0

This should give you a good starting point although it doesn't actually oscillate in Circuit Wizard simulations. Might oscillate if it was actually built. EDIT This shows the op amp operating on its own. I've changed the output stage to make it symmetrical which it'll probably need to be for the oscillator to work. The output stage could probably be ...


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