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Your transistor symbols are not placed in a matched manner. Make them identical, both in the top PChannel? diffpair and in the bottom Nchannel? current mirror. =============================================== Also, without I_V plots of the transistors (sweep the Vds 0 to 3 volts; step the gate with 0.1 volt steps from 0v to 1.5v; do for Vbulk_source = 0v, for ...


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Q point is the point where a non-linear circuit (like diodes, transistors, etc.) can be approximated by a linear circuit, and we get a DC set of voltage and current of that non-linear circuit.


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Following up on Bimpelrekkie answer, I see four choices Use longer channel devices Use cascading, where base(if bipolar) or gate(if fet) is held at some voltage below the Pch Sources, so the mirror device is in Saturation (stiff Iout) region; this may be needed to tolerate HIGH VOLTAGES; if you have wells for your Pch, this will allow operation up to the ...


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The output current will only be exactly the same as the input current when both transistors have exactly the same voltages across all terminals. Their \$V_{GS}\$ are the same as the gates and sources are in parallel. But what about the drain and \$V_{DS}\$? Hint: learn about "channel length modulation". Short channel, L = 0.5 um: the channel length ...


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You're confusing the BIOS ROM chip technology with the CMOS non-volatile user configuration data. PCs traditionally use EPROMS for the BIOS (now often stored in Flash memory instead and far easier to upgrade). Whether they are fabricated using CMOS or NMOS technology only affects their power usage. Whilst a CMOS EPROM may have lower operating current than an ...


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The Philips NXP Nexperia HC(T) User Guide says: 7.6 Input capacitance … is specified as 3.5 pF (typ.) and comprises package, bonding pad/interconnecting track, input protection diode and transistor gate capacitances. […] The initial decrease in capacitance as VI rises from zero or falls from 5 V is due to increased reverse bias on the protection diodes. The ...


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Sincw these input_capacitance spikes are occurring, in each case, at VDD/2 where typical CMOS inverter designs have Nchan and Pchan conductances tweaked via W/L to operate, I suspect these spikes are MILLER EFFECT capacitance multiplication and the FET's gate_drain overlap capacitances are modulated by higher and higher voltages at the drain.


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A reverse-biased semiconductor diode's capacitance is a function of voltage. This effect is used in the varactor or varicap diode, a voltage-dependent capacitor. Wikipedia has an illustration of this, showing that increasing bias narrows the depletion zone, decreasing capacitance.


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