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Signal names are isolated within VHDL modules. So there is no "connection" between same-named signals between modules. So it's perfectly acceptable to use the name "Temp_1" in different modules. The only way to connect is via ports.
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Not a flip but a slide noname combo USB connector:
The SilverStone CPU02 cable with a flip combo USB connector:
One OEM for these kinds of plug is Rego (thanks to @endolith for finding that).
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Although the first number represents the number of junctions in the device and the next letter (or two) represent the device type, the last four work as a serial number and do not carry any information directly. You need to look at a table to get the specific information about the device. In some circumstances, you may notice patterns in the numbering, like ...
1
Even sans information on the application, a quick search yields this obsolete part number (3–1734062–2):
The key word along with your verbal description is "offset" type.
While it's possible there are compatible versions from other manufacturers, it's also quite possible there are no current manufacturers of this part.
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To build:-
From https://www.moflon.com/mpcb.html
So I suggest either buy some carbon brushes and mount them yourself in a DIY holder thingie, or buy a full a cheepo slip ring like the Adafruit one.
Notice that the slip ring picture above uses four sets of brushes to maintain electrical connectivity and mitigate contact bounce.
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For industrial environments the way to go is fully isolated, since you don't know where your signal's ground come from. Also EMC requirements are quite stricter.
For example, your 4-20 input schematic is limited in common mode from the power supply ground. That will give issue when there is a severe ground surge or something. Also I don't see any kind of ...
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When creating components in VHDL and instantiating them in a source file, does it matter if component have outputs that have the same name.
For example component A has an output called Out_1 and component B has an output also called Out_1. They are nested in source files in a way that when I instantiate components A and B, I am assigning output values Out_1 ...
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