8

Here's how I do equal length differential pair routing in Eagle CAD: Name traces D_P and D_N (or something _N and _P - seems like Eagle CAD needs the suffix). Create net class in schematic and add both traces to it Route the traces, either together (the default) or separately (type ESC and Eagle CAD will stop routing the second trace). In board view, type ...


4

The rise/fall times are not that critical, no. As shown in the data sheet for the device you reference: Referring to Figure 33, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half ...


4

Unconstrain the output (set a false path) and the timing violation will go away. In Vivado you put these in the .xdc file for your design. More about that here: https://forums.xilinx.com/t5/Timing-Analysis/What-does-quot-set-false-path-through-quot-do/td-p/397531 set_false_path is part of the group of tcl commands called SDC, short for Synopsys Design ...


4

I am not aware of any tool having that option. The closest is the 'register balancing' support in e.g. Synopsys synthesis. There YOU put X register stages at the output and the tool pushes them into the design to get timing closure. I don't know in how far this is supported by synthesis tools from other vendors. What you are doing is absolutely incorrect!!! ...


3

First and foremost, timing constraints are not used to add logic. The purpose of these constraints is to tell the static timing analysis (STA) tools what your logic does. The emphasis is on your logic. It is your job as the designer of the circuit to add any pipelining that may be needed into the HDL yourself. Secondly, the set_multicycle_path is not ...


3

When using multicycles, you must be careful that the path is indeed multicycle-safe. In your case, the lack of clock-enable on capture_com_rx_packet_counter would make it "unsafe". It should be possible to force the synthesis tool to use a flip-flop primitive with a clock-en, which would be the first step to multicycle. However, while multicycle is very ...


3

Define divide by 1 clocks on the and_* nets and declare them to be physically exclusive. Cadence RTL compiler handles the situation correctly by generating 3 timing paths for registers clocked by cpu_clk (one path each for one clock). Registers directly driven by clk0, clk4 and clk_ext have their own timing arcs. create_generated_clock -source [get_ports ...


3

I'd say that the rule of thumb is: set either input port of the top module, or Q pin of an internal flip-flop as the source of generated clock. Example Verilog code: module top ( input clk, input rst, ... ); ... always @(posedge clk or negedge rst) begin if (rst == 1'b0) div_2_clk = 1'b0; else div_2_clk = ~div_2_clk; end ... ...


3

As you have surmised, you get errors when you have incompatible IO standards in the same bank. It's best to know exactly how this stuff works, because the tools will gladly give you a bitfile that ends up burning out your FPGA due to incompatible IO. As you posted above, we can consult the Xilinx datasheet for the device family, DS312. Supported IOSTANDARDs ...


2

There is a -regexp option for get_posts. Try: set_input_delay -clock [get_clock clk] 5000 [get_ports -regexp data_x\[\d+\]\[\d+\]\[\d+\]] You can get bus ports by their base name. Not sure it it works on multi-dimensional arrays. So this might also work: set_input_delay -clock [get_clock clk] 5000 [get_ports data_x]


2

The answer to that one is simple: both. If you violate either one you're in trouble. And just using these two will not allow a reliable estimate of maximum clock frequency. You also need, at a minimum, to factor in the propagation delay from clock edge to ouput change. Plus, and this is critical, you need to allow time for propagation of combinatorial delays....


2

OK, so after some try and error, here is how I managed to do it: First an AREA_GROUP which spans the part of the design which shall be constrained must be declared (in the projects UCF file). INST "my_module/*" AREA_GROUP="pblock_my_module"; This creates an AREA_GROUP containing everything in the design hierarchy "below" my_module. Now a range for the ...


2

A two flip-flop synchronizes can be constrained with the follwing XDC lines. XDC is a Xilinx flavor for the commonly known Synopsis Design Constraint files (SDC). set_property ASYNC_REG true [get_cells -regexp {gen\[\d+\]\.Sync/FF2}] set_property ASYNC_REG true [get_cells -regexp {gen\[\d+\]\.Sync/FF1_METASTABILITY_FFS}] set_false_path -from [all_clocks] -to ...


2

It is possible to differentiate the steps in LTspice by Right-Clicking on the waveform's label (in the waveform window) and then adding @x to the trace's expression, where x is the step's number. For example, for .step param x 1 5 2, plotting V(out)@1 will plot V(out) for the value x=1 (first step), V(out)@1 => x=3 (2nd step), and V(out)@3 => x=5 (3rd step). ...


2

As your FPGA and micro-controller run of different clocks, there is NO timing relation between them. To safely transfer data between them you have to use synchronizers or a circuit which has clock domain crossing logic built-in like an asynchronous FIFO with a read and write clock (Every FPGA vendor I known has IP for those). This also means that you can't (...


2

In my experience, Altium gets mixed up when vias are close together. When it says there is an un-routed net from via to via, try moving the vias farther apart (or make them smaller). You can also get more info about what Altium is thinking by going to Design -> Rules... and then select Electrical - Un-routed Net - UnroutedNet. In that dialog box, uncheck ...


2

The latching clock in your FPGA logic is a 130 degrees phase-leading version of the launching clock SCKB. You just have to provide this information correctly to Timing Analyser. From the timing report, it is observed that Timing Analyser considers launching edge at 6.5 ns, and latching edge at 10 ns. The path report indicates that Timing Analyzer thinks ...


1

The set_output_delay -min SDC syntax does this (Vivado XDC file.) You specify the 'min' value as a negative number as this event happens after the clock. (What's SDC? Stands for Synopsys Design Constraints, which Xilinx, Altera and others have adopted for specifying timing and other routing / synthesis constraints. With Vivado, SDC replaces the old Xilinx ...


1

First of all: The timing (maybe) is the most essential and hardest part of the FPGA development. So first I suggest to read/watch timing guides. Measuring technology: Of course, it is impossible to make mathematically equal delays. (What's more not just delay, any two quantity cannot be exactly equal.) So you need to define the ranges in between you can ...


1

Well, the power draw will be pretty dependent on how much power you're dumping into your load, varying the supply voltage would be a pretty simple way of regulating the power output of a resonant circuit.


1

The Virtex-5 XC5V110T is for example mounted onto the Xilinx XUPV5 board. This board is equivalent to the ML505 board: same pin-out, same external devices, but a "bigger" FPGA. All Xilinx references regarding the XUP5 board are listed here. The undocumented and incomplete Master UCF Pin Constraints file can be found on the same website. Our PoC-Library ...


1

One way is to define a FROM TO constraint, e.g. in UCF syntax: TIMEPSEC "TS_PAD2FF" = FROM PADS("my_ports") TO FFS("my_ffs") 4 ns; However, this does not define the maximum allowed difference of the path delays, but an absolute path delay for all paths from a group of pads to a group of FFs. So a possible fixed timing delay which all paths have in common ...


1

I to had this issue with ISE14.7 i was able to get the TIG by changing the NET to INST but the MAXDELAY can only be on a net. The output net from that instance is not (from PlanAhead) the same net name as the instance.


1

Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer. Choose File > New SDC file. The SDC editor opens. Type the following code into the editor: create_clock -period 20.000 -name osc_clk osc_clk derive_pll_clocks derive_clock_uncertainty Save this file as my_first_fpga_top.sdc (see Figure 1–38).


1

Setup time limits the fastest frequency (shortest period) for the clock. Hold time must be met to have proper operation, and any added buffers or delays to ensure hold time is met can slow the circuit below what you'd estimate from setup time. Beyond this simple rule of thumb, the upper frequency limit depends on the circuit details, and once you determine ...


1

Despite being fairly common in the industry to globally cut all paths between two clock groups, I would strongly advise against this practice as it makes it very hard to spot places where you unintentionally re-sampled a signal between clock domains. You are better off using a common block for transferring data between domains. Embed the constraints in the ...


Only top voted, non community-wiki answers of a minimum length are eligible