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4 votes
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Passing input on one pin of FPGA straight out to another output pin for monitoring

Unconstrain the output (set a false path) and the timing violation will go away. In Vivado you put these in the .xdc file for your design. More about that here: https://forums.xilinx.com/t5/Timing-...
hacktastical's user avatar
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4 votes

FPGA automatic pipelining?

I am not aware of any tool having that option. The closest is the 'register balancing' support in e.g. Synopsys synthesis. There YOU put X register stages at the output and the tool pushes them into ...
Oldfart's user avatar
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3 votes
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Timing parameters of sequential circuit - digital electronic

Your statement on \$T_{cQ,bb}\$ is correct. Take your operating conditions into account for minimum and maximum. You might need them for the next stages. Operating conditions include commonly load, ...
the busybee's user avatar
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3 votes
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FPGA automatic pipelining?

First and foremost, timing constraints are not used to add logic. The purpose of these constraints is to tell the static timing analysis (STA) tools what your logic does. The emphasis is on your logic....
Tom Carpenter's user avatar
3 votes
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LTSpice constraints on plots

It is possible to differentiate the steps in LTspice by Right-Clicking on the waveform's label (in the waveform window) and then adding @x to the trace's expression,...
a concerned citizen's user avatar
2 votes

Altium Unrouted Net in Fill

In my experience, Altium gets mixed up when vias are close together. When it says there is an un-routed net from via to via, try moving the vias farther apart (or make them smaller). You can also get ...
PhilG's user avatar
  • 21
2 votes

How to estimate timing contraints for FPGAs?

As your FPGA and micro-controller run of different clocks, there is NO timing relation between them. To safely transfer data between them you have to use synchronizers or a circuit which has clock ...
Oldfart's user avatar
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2 votes
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How to constrain a source-synchronous FPGA input?

Your exact timing requirements from the source seems a bit unclear? tsetup = 0.4 ns. thold = 0.5 ns. If you by these numbers really mean to say that the input signal is valid only during a 0.9ns ...
Timmy Brolin's user avatar
2 votes
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SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

The latching clock in your FPGA logic is a 130 degrees phase-leading version of the launching clock SCKB. You just have to provide this information correctly to ...
Mitu Raj's user avatar
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2 votes

Altium: Is it okay to waive this constraint violation between two elements of the same electrical component?

The violation is presented because these pads are closer than 0.127 mm (not because they are 0.127mm apart). This can be rectified a number of ways, deciding which to pick is up to you (consider costs ...
Attie's user avatar
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2 votes

Altium: Is it okay to waive this constraint violation between two elements of the same electrical component?

The reason for the violation is that the two pads provide less clearance than the constraints that you have set up. Either modify the footprint to suit the necessary constraints (if possible, ...
Klas-Kenny's user avatar
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1 vote

FPGA output timing explained

It seems that in my case the output clock is inverted. Therefore leaving me 5[ns] before and after the edge. So 3[ns] for the setup time and 4[ns] for the hold time. Here the propagation delay inside ...
Dukel's user avatar
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1 vote

Best practice to constrain dynamically tuned FPGA->DAC data path

The programmable delays represent timing uncertainty. Registering the input signals as soon as possible would be good practice so that the timing uncertainty doesn't propagate further into the design. ...
user4574's user avatar
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1 vote
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How can I declare individual PMOD pins as input or output in an FPGA?

The solution is to split JA into 2 different ports (notice the JA1): ...
Martel's user avatar
  • 1,259
1 vote
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FPGA Timing Constraints

As some of the commenters observed, timing analysis can be a very complex topic. In this answer, I will try to hit some of the important and practical points. Q: Why is it important to constrain ...
Troutdog's user avatar
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1 vote
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Use SDC format for timing constraints on Xilinx CPLDs

AFAIK, you can only use .sdc files with Synplify synthesis, not with ISE synthesis. If you're using ISE synthesis, then you'll have to find or create a way to translate .sdc to .ucf or .xcf I've never ...
Dave Tweed's user avatar
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1 vote

SDC constraint inside Xilinx ISE

Two comments. It may be time to consider upgrading to Vivado. ISE is nearing its end of life for the Xilinx FPGA families When you have a defined clock boundary crossing a common way to flag that in ...
hacktastical's user avatar
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1 vote

How to correctly constrain a clock network with lots of mux branches?

Quite tricky and a bit complex. What I would have done is (SDC Contraints): Constraint clocks src_1 to src_N using: ...
Mitu Raj's user avatar
  • 11k
1 vote

Unable to constrain HPS peripheral pins on intel agilex fpga dev kit

I found the issue and like to share the solution in case someone else might end up having this issue. I rely on custom pin layouts for the HPS periphery in the IP settings in order to constrain the ...
Doralitze's user avatar
1 vote

SystemVerilog randomization for a fixed sequence of values

You can use the post_randomize function to increment the count: ...
toolic's user avatar
  • 8,561
1 vote

Constrain plane clearance from annular ring in Altium

We worked around inadequate constraints for power planes by implementing the layer as a pour instead. Pours are subject to the more comprehensive constraints that apply to polygons (see ...
Joel's user avatar
  • 21
1 vote

Vivado : constraints setup for SPI interface with common clock

First of all: The timing (maybe) is the most essential and hardest part of the FPGA development. So first I suggest to read/watch timing guides. Measuring technology: Of course, it is impossible to ...
betontalpfa's user avatar
1 vote

Lower Power Inductive Heating Circuit Design Questions

Well, the power draw will be pretty dependent on how much power you're dumping into your load, varying the supply voltage would be a pretty simple way of regulating the power output of a resonant ...
Sam's user avatar
  • 3,759
1 vote

How to specify a minimum clock to output time in output timing constrain?

The set_output_delay -min SDC syntax does this (Vivado XDC file.) You specify the 'min' value as a negative number as this event happens after the clock. (What's SDC? Stands for Synopsys Design ...
hacktastical's user avatar
  • 54.8k
1 vote

Understanding timing constraints

Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer. Choose File > New SDC file. The SDC editor opens. Type the following code into the editor: ...
Cristian Mardones's user avatar

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