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In your set_output_delay -min statement, just enter the hold time as a negative value, like this: set_output_delay -clock <clock> -min -<hold time> <port> Have a look here: http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/ Here too: https://forums.xilinx.com/t5/Timing-Analysis/How-to-set-input-delay-and-output-delay-when-...


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The set_output_delay -min SDC syntax does this (Vivado XDC file.) You specify the 'min' value as a negative number as this event happens after the clock. (What's SDC? Stands for Synopsys Design Constraints, which Xilinx, Altera and others have adopted for specifying timing and other routing / synthesis constraints. With Vivado, SDC replaces the old Xilinx ...


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