New answers tagged cortex-m
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Why does ATSAM3X8E have two separate registers for setting and clearing bits?
To expand upon the mention of atomic operations in the answer, the ATSAM3X8E datasheet shows that microcontroller incorporates the ARM Cortex-M3 Bit-banding:
The regions for SRAM and peripherals ...
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Why does ATSAM3X8E have two separate registers for setting and clearing bits?
Just to add to @Justme's answer, this especially important on registers whose contents are modified by the microcontroller.Imagine an interrupt status register (that contains multiple interrupt ...
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How does ATSAM3X8E's SAM-BA bootloader work?
The SAM3X8E can be configured to boot to SAM-BA monitor (the default), or to Flash 0 or 1. This is done via the GPNVM bits and is described in section 7.2.4 of the datasheet. Setting GPNVM1 to 1 ...
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Why does ATSAM3X8E have two separate registers for setting and clearing bits?
If you want to enable one pin, you write the bit 1 which pin you want to enable. The bits that are 0 do nothing.
So your example with single enable is OK.
Your second enable might be completely wrong ...
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CORTEX-M jump causes UFSR=2
Let's look at ARM's AN209 "Using Cortex-M3/M4/M7 Fault Exceptions":
INVSTATE: [...] the processor has attempted to execute an instruction that makes illegal use of the Execution Program ...
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